Hacker News Reader

AMD says "256-bit LPDDR5x"

It might be technically correct to call it 8 channels of LPDDR5 but 256-bits would only be 4 channels of DDR5.

DDR5 uses 32bit channels as well. A DDR5 DIMM holds two channels accessed separately.

Thank you for the correction: I didn't realize each DDR5 transaction was only 32 bits.

Per above, you need 272GB to run Qwen3-Coder (at 4 bit quantization).

wrong it is approx half bandwith