Silicon is way outside my wheelhouse, so genuine question: why not mention power consumption? In the data center, is this not one of the most important metrics?
How about "longer battery life".
Also "lower cost".
Or sacrificing those on the alter of more compute running more complex things.
For instance, GK104 on 28nm was 3.5 billion transistors. AD104 today is 35 billion. Is Nvidia really paying 10x as much for an AD104 die as a GK104 die?
What google turns up when I google this is this statement by google [1], which attributes the low point to 28nm (as of 2023)... and I tend to agree with the person you are responding to that that doesn't pass the sniff test...
[1] https://www.semiconductor-digest.com/moores-law-indeed-stopp...
There's significant demand for older process nodes and we constantly see new chips designed for older nodes, and those companies are usually saving money by doing so (it's rare for a new chip to require such high production volumes that it couldn't be made with the production capacity of leading-edge fabs).
Intel and AMD have both been selling for years chiplet-based processors that mix old and newer fab processes, using older cheaper nodes to make the parts of the processor that see little benefit from the latest and greatest nodes (eg. IO controllers) while using the newer nodes only for the performance-critical CPU cores. (Numerous small chiplets vs one large chip also helps with yields, but we don't see as many designs doing lots of chiplets on the same node.)
My phone dies much faster when I am using it, but admittedly screen usage means I can't prove that's chip power consumption.
VR headsets get noticeably hot in use, and I'm all but certain that that is largely chip power usage.
Macbook airs are the same speed as macbook pros until they thermally throttle, because the chips use too much power.
This claim just doesn't pass the smell test.
Why wouldn’t you want lower power usage?
It'll be beneficial to DRAM chips, allowing for higher density memory. And it'll be beneficial to GPGPUs, allowing for more GPU processors in a package.
SRAM is probably the the worst example as it scales poorly with process shrinks. There are tricks still left in the bag to deal with this, like GAA, but caches and SRAM cells are not the headline here. It's power and general transistor density.
For data centers, it will help a lot. More compute for same power.