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Comment by dragontamer | Hacker News Reader

> Yet CPU ISAs of today are not really that different, conceptually.

CPU true.

GPU no. It's not even the instructions that are different, but I would suggest studying up on GPU loads/stores.

GPUs have fundamentally altered how loads/stores have worked. Yes it's a SIMD load (aka gather operation) which has been around since the 80s. But the routing of that data includes highly optimized broadcast patterns and or butterfly routing or crossbars (which allows for an arbitrary shuffle within log2(n)).

Load(same memory location) across GPU Threads (or SimD lanes) compiles as a single broadcast.

Load(consecutive memory location) across consecutive SIMD lanes is also efficient.

Load(arbitrary) is doable but slower. The crossbar will be taxed.

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One of the Hennessy/Patterson books has coverage of GPUs. But the definitive description of GPUs at a conceptual undergrad level has yet to be written, I think.

As for microarchitectures, for the most part those have evolved over the last 50 years. If you are looking to extract the last bit of speed out of a CPU, the only complete resource is the documentation. But pipelines and caches have heen around for a long time, look at the System/360 Model 85 and 91. A C programmer can use a fairly primitive conceptual model of a microarchitecture to get a pretty good first-order approximation of performance issues.

I am not saying that we should teach undergrads with 1980s materials. I am saying that a good understanding of pretty much any assembly language can get a programmer pretty far.

Do you have any good resources that go into detail on GPU ISAs or GPU architecture? There's certainly a lot available for CPUs, but the resources I’ve found for GPUs mostly focus on how they differ from CPUs and how their ISAs are tailored to the GPU's specific goals.

Unfortunately this is a topic that isn't open enough, and architectures change rather quickly so you're always chasing the rabbit. That being said:

RDNA architecture (a few gens old) slides has some breadcrumbs: https://gpuopen.com/download/RDNA_Architecture_public.pdf

AMD also publishes its ISAs, but I don't think you'll be able to extract much from a reference-style document: https://gpuopen.com/amd-gpu-architecture-programming-documen...

Books on CUDA/HIP also go into some detail of the underlying architecture. Some slides from NV:

https://gfxcourses.stanford.edu/cs149/fall21content/media/gp...

Edit: I should say that Apple also publishes decent stuff. See the link here and the stuff linked at the bottom of the page. But note that now you're in UMA/TBDR territory; discrete GPUs work considerably differently: https://developer.apple.com/videos/play/wwdc2020/10602/

If anyone has more suggestions, please share.

Branch Education apparently decapped and scanned a GA102 (Nvidia 30 series) for the following video: https://www.youtube.com/watch?v=h9Z4oGN89MU. The beginning is very basic, but the content ramps up quickly.

I assume most people learn microarchitecture for performance reasons.

At which point, the question you are really asking is what aspects of assembly are important for performance.

Answer: there are multiple GPU Matrix Multiplication examples covering channels (especially channel conflicts), load/store alignment, memory movement and more. That should cover the issue I talked about earlier.

Optimization guides help. I know it's 10+ years old, but I think AMDs OpenCL optimization guides was easy to read and follow, and still modern enough to cover most of today's architectures.

Beyond that, you'll have to see conferences about DirectX12 new instructions (wave instructions, ballot/voting, etc. etc) and their performance implications.

It's a mixed bag, everyone knows one or two ways of optimization but learning all of them requires lots of study.

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