I've worked on some of the current highest profile chip projects doing "frontend" RTL design, and at every major chip company I've worked at, and from talking with coworkers about their past experiences at other companies, the handoff-wall between RTL and PD is leaving a substantial amount of perf per power/area on the table. (like 30% I'm general)
RTL designers generally have no visibility into how their designs are getting laid out, and generally don't want to have to care. PD engineers have no visibility into the uArch and low level code details, and maybe they want to care but everything is too obfuscated in general.
So when your pins are misplaced during an early iteration, RTL will blindly add retiming to resolve timing issues and make PD happy but never check if it's actually needed. PD will slave away trying to make busted RTL work with placement and recipe adjustments rather than asking RTL for a trivial fix, etc etc.
There are a ton of small things where visibility into either side of the process would result in measurably better hardware, but the current team structures and responsibility boundaries encourage people not to care.