Development of a transputer ISA board
nanochess.org
nanochess.org
I wonder why he used the 74LS00 family instead of 74HCT00, even if he really needed the TTL thresholds? I forget if ISA even requires TTL levels. Is that a question of nostalgia, or is there a practical advantage of TTL over TTL-compatible CMOS in this context that I'm unaware of?
You cannot choose the source, these come mixed from ST, TI, and other manufacturers. I preferred the laser-engraved ones instead of the white ink ones just to have an uniform look.
The crystal oscillator needs something faster so it requires 74F04, and the link communication buffer requires 74F244 or 74AS244. These are more expensive, the 74F are 2 dollars each chip, and the 74AS are 4 dollars each chip.
The electronics parts stores in my town (Morón), which are several blocks from my house, have a fairly limited part selection, mostly for repair purposes. So part availability is a very significant concern. I was shocked to find last month that one of them didn't even have a TL431! But another one on the same block did.
I thought I'd check Digi-Key, but it seems like 74AS244 is even more than US$4 there in onesies: https://www.digikey.com/en/products/detail/texas-instruments.... However, a CMOS 74AHC244 (nominally something like 5.5ns to the AS244's 6.2ns) is only 27¢: https://www.digikey.com/en/products/detail/texas-instruments...
At Digi-Key, the CMOS parts have better availability in this case, but that says nothing about the availability at the corner store.
Thank you for explaining!
with latest (eg TSMC) processes, someone could build a regular array of 32-bit FP transputers (T800 equivalent):
- 8000 CPUs in same die area as Apple M2 (16 TIPS) (ie. 36x faster than an M2)
- 40000 CPUs in single reticle (80 TIPS)
- 4.5M CPUs per 300mm wafer (10 PIPS)
heat would be the biggest issue ... but >>50% of each CPU is low power (local) memory
nevertheless, coding an array of RISC CPUs in an HLL is far easier and would have a broader base than hand tuned, machine specific CUDA
we have to zoom out from the 1980s when 4 CPUs were a lot ... but now you can build 40,000 (ie 200 x 200 array) of CPUs within the single reticle limit (ie same as a big NVIDIA) then a big MIMD must be coded with algorithmic patterns like map-reduce, pipelining, etc.
but the general CPU nature and HLL coding means that this is far easier than CUDA to get close to theoretical max performance
[1] or any CSP with both input and output descheduling - ie no queueing
i want all 64 bits with a write strobe and a 3ghz clock. let me blink leds by bitbanging /dev/mem
SCSI was already contending with the termination problem in the early 90s; low-voltage differential SCSI was in the SCSI-3 standard from 01995, 30 years ago, in order to hit 80 megabytes per second over the kind of multidrop (bus) parallel interface you're talking about. That's twenty thousand times slower than the main system memory interface on the latest amd64 servers.
At the point where you already had to go to low-voltage differential signaling to get reliable communication, your bus is no longer a useful GPIO interface for blinking LEDs.
But if you have a 50¢ 16-line GPIO expander chip like https://www.digikey.com/en/products/detail/kinetic-technolog... somewhere on the SMBus the board is already using for things like temperature monitoring, maybe for some other minor interface function, all that's required is to run its GPIOs to test points and document them. Not as fast as the ISA bus but plenty of power for simple digital interfacing.