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Quite slow. It's largely due to the author using FPGAs wrong. Clocking down a 7-series Artix to 62.5 MHz means the design is not pipelined correctly/enough. My friend got 1 SHA256 hash per cycle at 300 MHz on 7 series, but slightly fewer of the design fit on a chip. Thruput would easily be in the GH/s range.

Keep in mind RTX4090 is 5 nm process node and has a lot more transistors and memory than XC7A100T, which is 28 nm. That's a huge difference in terms of dynamic performance. Also, the two are also released 10 years apart. If you compare RTX4090 against a similarly modern UltraScale part from Xilinx, I believe the FPGA can be notably faster than RTX4090.

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I'm assuming this space has already been heavily optimized by the Bitcoin miners on their way to ASICs.

Yes, hard silicon will be another magnitude more performant than FPGAs and GPUs, but ASICs properly take on negative value when they're no longer profitable to mine with. (Note that efficiency won't be much better at the same process node. You can just pump more power through each ASIC die)

Edit - I misread your comment. ASIC designers will use FPGAs to test their design but it won't be optimized for FPGAs which have a different logic-and-memory characteristic than ASICs. There aren't many great SHA256 FPGA implementations, largely because there's not that much demand for one

> but ASICs properly take on negative value when they're no longer profitable to mine with

No matmul coin where the hardware could be repurposed for AI stuff?

Modern BTC ASICs consist of 1600-3200 SHA256 cores and only output nonces for sha256(sha256(btcBlockHeader)) - there's no memory or ability to obtain other output.

always thought it might be cool to repurpose fast double sha engines for error detection in storage arrays

matmul isn't a trapdoor function

Unfortunately I think most of that innovation happened behind closed doors, because everyone wanted to maintain their competitive advantages.

Yes, ASICS are definitely very closed source for that specific reason.

Yes, but a designed-for-FPGA SHA256 implementation looks very different than an ASIC SHA256 implementation - the ASIC has far greater routing flexibility and density, and can therefore use far more combinatorial logic between register stages.

(ASIC simulation on an FPGA will retain the combinatorial stages but run at dramatically lower fMax)

I should have been a little clearer. I meant that the miners spent a brief period optimizing FPGAs before they abandoned them entirely for ASICs, but during that brief period I'm guessing they squeezed as many hashes/watt out of the FPGAs as they could.

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