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Comment by amszmidt | Hacker News Reader

Mostly dead. Current Lisp Machine shenanigans related to MIT/LMI are at https://tumbleweed.nu/lm-3 ...

Currently working on an accurate model of the MIT CADR in VHDL, and merging the various System source trees into one that should work for Lambda, and CADR.

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> Currently working on an accurate model of the MIT CADR in VHDL

Sounds extremely interesting, any links/feeds one could follow the progress at?

The dream of running lisp on hardware made for lisp lives on, against all odds :)

Current work is at http://github.com/ams/cadr4

And of course .. https://tumbleweed.nu/lm-3 .

Maybe try replacing the ALU with one written directly in Verilog, I suspect this will run a lot faster than building it up from 74181+74182 components.

From what I see -- that is not the case.

The current state is _very_ fast in simulation to the point where it is uninteresting (there are other things to figure out) to write something as a behavioral model of the '181/'182.

~100 microcode instructions takes about 0.1 seconds to run.

I was thinking more of a behavioral model of the whole ALU, just so that the FPGA tools can map it onto a collection of the smaller ALUs built into each slice.

What clock speed does your latest design synthesize at?

At the top of the readme it says "There will be no attempt at making this synthesizable (at this time)!".

There was already a design of CADR for FPGAs [1] that does synthesize (and boot), I don't know why amszmidt needed to start again from scratch or if his design is a modification of the earlier one.

A similar comment applies to lm-3. Maybe it is built on a fork of the previous repo, it is hard to tell.

[1] https://github.com/lisper/cpus-caddr

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