Characterizing my first attempt at copper-only passives | Hacker News Reader

Characterizing my first attempt at copper-only passives

moroso.emarhavil.com

32 pointstverbeure9 comments

When I first started doing microstrip RF distributed elements like UHF notch filters I was really confused by the results I was getting from my $400 pocketVNA. The microstrip filters worked when I had them in my physical RF pipeline but the S11 I was measuring was crazy. Eventually I gave up.

One day while complaining on IRC someone suggested I let the VNA warm up before doing the calibration routine. I'd just been doing it right after turning it on because naturally, that's what was required first. I waited 15 minutes and then did the calibration. Suddenly the S11 plots actually matched the behavior and I could compare directly against the sonnet fullwave sim design instead of just "it seems to work".

With only several dollars worth of high-precision PCB specifications, you two can save multiple fractions of a cent worth of passive components!

There are applications where this can be useful, though. Especially when PCB production quirks can be more repeatable than component soldering, which can be affected by ambient temperature, humidity, solder paste age, and a bunch of other factors.

I think that if you care about a 2pF cap then you need to understand the parasitics in your board anyway

You can also build much lower inductance bypass caps with your internal power planes than you can get out of any component!

As a relative newcomer to radio design, please expand on this with layout graphics and methodology.

I don't have the bandwidth to generate graphics (and this is necessarily very application-specific), but here's the general gist:

A PCB stackup has multiple layers of metal with dielectric material sandwiched between them. In a 6+-layer PCB, it might be reasonable to have multiple power and ground planes (sheets of copper) at a close spacing. If you refer back to your electronic component geometries, we can see this as a parallel-plate capacitor.

Say your plane spacing is 0.2mm (2x10e-4 m) and your dielectric constant is ~4. That would make the planes a capacitor with value ~1.6x10e-14F/mm^2 or ~0.16 pF/mm^2. That may not seem like much, but it means the capacitance under a 1cm^2 chip is 16pF, and the impedance at 100 MHz is ~100Ω. Because the chip can then have very short (sub-mm) vias as its entire trace to power, the inductance is also very low.

This is a good resource for a deeper dive: https://docs.amd.com/r/en-US/ug583-ultrascale-pcb-design/Pla...

Perfect thanks

People do that inside silicon chips. I searched in some of the old posts by kens:

Resistors: https://www.righto.com/2022/01/silicon-die-teardown-look-ins...

Capacitors: https://www.righto.com/2018/06/silicon-die-analysis-op-amp-w...

It gets done inside silicon chips because the (relative) costs of going off the chip and back on again are huge, and the parasitic inductance of the on/off chip path can make a an off-chip capacitor effectively useless.

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