Personally these days I would lean towards the ESP32, they continue to iterate on it nicely and it has great community support. I'm personally developing a smart watch platform based on micropython.
Getting down to 10mAh is not so bad. If you're not actively driving the display, you can under-clock significantly [1], if you're not using WiFi you can turn the modem off [2].
[1] https://docs.espressif.com/projects/esp-idf/en/stable/esp32/...
[2] https://docs.espressif.com/projects/esp-idf/en/stable/esp32/...
Also 20 hours of runtime is horrible.
There are many ESP32 variants, depending on what you pick some may be more compelling for your use-case.
Even some newer variant like S3 or C6 only has acceptable power consumption, if what you are after is run-time they are not the best fit.
PineTime, based on NRF52, will get you 4-7 days of practical usage.
Recently they release ESP32P4, with very strong performance, but like you guess, without Radio
I think once we start talking about GPU, MMU, USB, display, etc, we're getting towards a CPU of sorts.
Speaking of a low-end CPU, I want to test out the RV1103 Rockchip, those crazy little chips are running Linux apparently [1], and even able to run Python [2]. Depending on power draw, a Linux-based smart watch could be on the horizon.
[1] http://wiki.osll.ru/doku.php/etc:users:jcmvbkbc:linux-xtensa...
For ex: Bes2700bp and bes2800 has 3d GPU iirc. Their spec is very impressive, too bad that their SDK is kind of limited to non-Chinese vendor
The low power chips can also run in low power mode without BLE running using micro amps, something the ESP can’t match.
I really like ESP32 and I hope they have a low power chip on their roadmap.
Years ago I had a "smart" watch that had a sim card and was a full mobile phone within its own right, I think it was just 10 years or so too early.
And this chip isn't a normal QSPI chip where you read the datasheet. You have to use NRF connect, and Zephyr.
So, this brings up the obvious question: What if I don't want my whole firmware to be Zephyr nRF-connect, just for a Wi-Fi chip?
From the CPU perspective, they are the same
Depends!
If the two chips use UART or SPI for intercommunication, okay, you need two lines between the CPU and two GPIO lines for wakeup, and JTAG can be shared anyway.
But if you use stuff like shared memory, or want to do stuff like updating the display not just from the high-power chip but also from the low-power one, suddenly design becomes much more complex.
Most contemporary SoCs will have more memory (and compute power) than that.
Instead there's a massive gap between Linux-capable systems and RTOS-focused systems despite, like you said, the latter now being bigger and better than real shared UNIX systems.