The complicated circuitry for the 386 processor's registers

That additional type ‘a’ register, supporting copying directly from the type ‘b’, is intriguing. I can well imagine the article to be correct that it’s a place to stash ESP during interrupt stack setup, specifically if there’s a privilege transition since I would think it’d be easier from an implementation point of view to “simply” copy ESP to that special register, load the new ESP from the TSS, and then stack that special register after stacking SS using the usual stacking logic.

Though of course that then raises the question of how SS itself is handled, since something similar would be needed there I think.

They're only mentioned for the 80386 version of the LOADALL instruction though, where he confirmed that the CPU actually does bus cycles to read them. But the same registers already existed on the 80286 (only 16 bits of course). On that chip they are the 3 words before and 7 words after the MSW, the ones marked as "None" in the table there (note that it is slightly wrong, MSW should be 806H instead of 804H).