Well I think both commentators are valid- the effect of shrinking a transistor but keeping the same geometry is probably well captured by this model. Going from a "10 nm" DUV finFET to a "7 nm" EUV finFET, this model probably works quite well whether you're manufacturing using EUV or DUV.

I think the crux of the matter is the transition from 7 nm down to our modern nodes, where the major change was not only going from DUV to EUV, but perhaps more importantly the change from finFET to multi-gate or gate-all-around FET (GAAFET), where this model probably needs significant updates to be still valid.