Looks like they're claiming everything under the sun for 3). https://github.com/siliconcompiler/logiklib/blob/main/logikl... and https://www.zeroasic.com/fpga-architect say more. I'm very skeptical though. They claim binary compatibility? I don't know what that means for an FPGA. They seem to be testing all CLB vs some DSP/BRAM macros. What does it mean to have binary compatibility between those? Usually you don't want that. The design should be optimized for the device it's on. I don't want to take an fmax hit because someone may be using a soft multiply or something like that. Only time will tell.