Show HN: Penguin-rtl – Verilog equivalence checking locally in the browser

Hi HN! I made this little web app for formal equivalence checking of Verilog that runs totally locally in the browser.

I initially wrote it for myself to (confidently) rewrite clumps of combinational logic. The idea is that the same logic can be implemented in many ways, but not all will map optimally to FPGA resources.

This is also something I wish I had during my digital design class, so I'd be thrilled if a student found some use of it.

It’s powered by YoWASP, a WASM package of Yosys. Yosys is an open-source logic synthesis tool with extensive Verilog-2005 support and built-in formal verification capabilities.

Yosys also has some interesting work in verification for designs with sequential elements, which I’ll be exploring next. I’m also looking into SystemVerilog/VHDL support using plugins.

Happy verifying!