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Comment by dcan | Hacker News Reader

To be more precise, four CPUs - two ARM and two RISC. There is just a mux for the instruction and data buses - see chapter 3 of the [datasheet](https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.p...).

It’s space-inefficient as half of the CPUs are shutdown, but architecturally it’s all on the same bus.

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> It’s space-inefficient as half of the CPUs are shutdown

In practice is doesn't matter very much for a design like this. The size is already limited to a certain minimum to provide enough perimeter area to provide wire bonding area for all of the pins, so they can fill up the middle with whatever they want.

They should have filled it with more SRAM instead - 520KB is far too little.

What difference would the extra 16KiB or whatever instead of the 2 RISC-V cores make? If 520KB is far too little for you, you're likely better off adding a 8 MiB PSRAM chip.

Just 16KB? Couldn’t a lot more be fitted?

PSRAM has huge latency.

SRAM takes up a tremendous amount of space compared to logic. Usually at least six transistors per bit, plus passives, plus management logic.

SRAM is big in gate count. typically 6 transistors per bit.

The i386, a 32 bit chip already dragging around a couple of generations of legacy architecture came in at 275,000. I would imagine the Hazard3 would be quite a bit more efficient in transistor usage due to architecture.

16K is 16384(bytes) *8(bits per byte) *6(transistors per bit) = 786, 432

It was the first CPU on my desk! 80386SX 25MHz.

(this one, only 32bit internally)

Thanks for the explanations - was not aware.

…vertically stack a slab of SRAM above or beneath the CPU die, does come to mind ;)

This is way too expensive for something like a microcontroller. AMD calls this 3D V-Cache and uses it on their top end SKUs.

But doesn't the ESP32-S3-WROOM have some large on-chip RAM?

For the Pico, say, something in the line of the approach taken by many smartphone SoCs that package memory and processor together.

The ESP32-S3 has 512 KB of SRAM, and the RP2350 has 520 KB of SRAM. The ESP32-S3-WROOM does indeed come in configurations with additional PSRAM, but that would be comparing apples and pears. The WROOM is an entire module complete with program flash, PSRAM, crystal oscillator etc. It comes in a much larger footprint than the actual ESP32-S3, and it is entirely conceivable that one could create a similar module with the same amount of PSRAM using the RP2350.

Furthermore, the added RAM in both cases is indeed PSRAM. That being said, the ESP32-S3 supports octal PSRAM, not just quad PSRAM, which does make a difference for the throughput.

> "some"

And go cellphone style: Package-on-Package or Multi-Chip Module of some sort.

Wouldn't the massive increase in capabilities from adding 8MB-16MB of closely-integrated, fast RAM far outweigh the modest price increase for many applications that are currently memory-constrained on the Pico?

> But doesn't the ESP32-S3-WROOM have some large on-chip RAM?

They use the same PSRAM chips with relatively bad latency you complained about higher up in the thread. There are boards like those from Pimoroni that even have them on the PCB from the factory.

> For the Pico, say, something in the line of the approach taken by many smartphone SoCs that package memory and processor together.

What for? This only saves you PCB space, the latency is not going to be affected by this. There probably won't be enough people ordering those to justify the additional inventory overhead of (at least) 2 more skews.

I believe there's already a separate Flash die in the same package. Probably not possible to add yet another die for DRAM.

(for various chemistry reasons, it's much more efficient to manufacture Flash, DRAM, and regular logic on separate wafers with different processing)

It may be technically space inefficient but they only added the RISC-V cores because they had area to spare. It didn't cost them much.

I wonder if they're using the same die for one or more microprocessor products that are RISC-V-only or ARM-only? They could be binning dies that fail testing on one or the other cores that way. Such a product might be getting sold under an entirely different brand name too.

That may be the plan for the future. Right now, this is a hedge / leverage against negotiations with ARM. For developers looking to test their code against a new architecture and compare it to known good code/behavior, it doesn’t get any easier than rebooting into the other core!

They're not currently doing that but there is a documented way to permanently disable the ARM cores, so they could sell a cheaper RISC-V-only version of the same silicon if there's enough demand to justify another SKU.

Source for the RISC-V cores being essentially free (Luke Wren is the creator of the RISC-V core design used):

> The final die size would likely have been exactly the same with the Hazard3 removed, as std cell logic is compressible, and there is some rounding on the die dimensions due to constraints on the pad ring design.

https://nitter.space/wren6991/status/1821582405188350417

Funny thing is that it cost them more than you might think. It was the ability to switch to the riscv which made it (much) easier to glitch. See the "Hazardous threes" exploit [1]

[1] https://www.raspberrypi.com/news/security-through-transparen...

I find this whole concept remarkable, and somewhat puzzling.

Have seen the same (ARM + RISC-V cores) even at larger scales before (Milk-V Duo @1GHz-ish). But how is this economical? Is die space that cheap? Could you not market the same thing as quadcore with just minor design changes, or would that be too hard because of power budget/bus bandwidth reasons?

two things:

1) it needs a certain perimeter to allow all the pins to go from the silicon to the package, which mandates a certain sized square-ish die 2) only the cores are duplicated (and some switching thing is added)

so yes, there is enough space to just add another two cores without any worries, since they don't need more IO or pins or memory or anything.

SRAM is very area intensive. What you're asking for is very greedy. The RISC-V core they are using is absolutely tiny.

Thats also a good point. For the big Milk-V systems I mentioned they use external DRAM-- but cache might still be a die-space issue (I'd assume that it's always shared completely between ARM/RISC-V cores, and would need to be scaled up for true multicore operation).

But I'm still amazed that this is a thing, and you can apparently just throw a full core for a different architecture on a microcontroller at basically no cost :O

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