Sorting algorithms with CUDA
ashwanirathee.com
ashwanirathee.com
Linebender is working (slowly) on adapting these ideas to GPUs more portably. There's a wiki page here with some resources:
Onesweep GitHub repo: https://github.com/b0nes164/GPUSorting
What, exactly, is misleading? The title of the blogpost is "Sorting Algorithms with CUDA" and I didn't get the feeling that the author is touting their "Bottom-up iterative merge sort" is the fastest possible way of sorting with CUDA. There is even a "Future Work" section at the end, implying even the author know it can be done better.
If author is taking a truly academic perspective, then a section should be included with background on state of the art, best known performance, etc.
If this is just a blog post (which is more likely) with less rigor, then the style could reflect that better. For instance, calling it an "introduction" or "exercise".
How many academic papers start with "I went for a NVIDIA recruiting event some days ago, that was a great event and it motivated me to try to rewrite the sorting algorithms using CUDA."
A very readable explanation is here: https://gpuopen.com/download/publications/Introduction_to_GP...
It turns out that radix sort can be implemented in a way that is very straightforward to parallelize. It's a beautiful and elegant approach and worth knowing about!
structs containing strings and doubles for example are well suited to radix sort.
Technically floats qualify, but not in an interesting way since you basically just need to take care of the sign bit and a few special cases.
Really most things can be sorted with radix sort, though I wouldn't want to be the one having to implement it for unicode strings (sorting text in general is one of those problems you'd preferably let other people solve for you).
You may also want to look at other sorting algorithms - common CPU sorting algorithms are hard to maximize GPU hardware with - a network sort like bitonic sorting involves more work (and you have to pad to a power of 2) but often runs much faster on parallel hardware.
I had a fairly naive implementation that would sort 10M in around 10ms on an H100. I'm sure with more work they can get quite a bit faster, but they need to be fairly big to make up for the kernel launch overhead.
[1] https://futhark-lang.org/ [2] https://futhark-lang.org/examples/merge-sort.html
If your job involves a lot of heavy number crunching it might be useful.
As for number crunching, I'd probably use CuPy (outside of the typical ML stuff).
Although on second thought something like JAX is probably the better choice these days anyway.
> there's literally nothing interesting here at all to most people who would be attracted by the title
is not some kind of judgment.
https://github.com/jedbrooke/cuda_bwt
I believe I got the implementation for bitonic sort here: https://gist.github.com/mre/1392067
Shameless plug for my own little post going a bit into the performance benefits of "vectorized" sorting, even vs. programmable L1 cache: https://winwang.blog/posts/bitonic-sort/
It's great since it easily works with the Cuda driver API, unlike CUB which is mostly exclusive for the runtime API. It also has Onesweep but I havent been able to make that one work.
thrust::sort is an Nvidia C++ library; I am not clear whether it is related to CUDA or not actually; the article author started out with CUDA implementing a merge sort, but once it was slower than CPU the author tried thrust::sort library and was able to get a faster result in some cases. The article author did not yet try a parallel merge sort.
I would be curious if anyone knows what database engines take advantage of GPUs and see actual sort/query performance boosts and on what sized datasets. My impression is that a few engines have tried it, but the payoff is small enough that industry-wide people haven't adopted it.
2. For typical applications, memory transfer speed matters more than sorting performance on the GPU. If most of your work is done on the CPU, transfering the memory to the GPU may take more time than sorting the array. Not sure if unified memory (apple M series chips and AMD new APU) can remedy this though.
As far as I can tell, it's less so that the payoff is small, but that the payoff is small considering the maturity/scarcity of GPU programming, and availability of GPUs (esp. on-prem).
Every database co-processor, not just GPUs, have had the same issue.