Orange Pi RV2 is a single-board PC with an 8-core RISC-V processor
liliputing.com
liliputing.com
SoC – Ky X1
CPU – 8-core 64-bit RISC-V processor
GPU – Not mentioned
VPU – Not mentioned
AI Accelerator – 2 TOPSIf it's the same as K1/M1 then ok, 512 MB L2 per 4 core cluster is simply inadequate for a normal Linux workstation workload.
I don't know where they (or SpacemiT) get the "30% faster than A55" claim because I certainly haven't seen any such thing. On some micro benchmarks such as my own primes one the K1 comes in at slightly more clock cycles than the U74 in JH7110, but pulls slightly ahead on high clock speed. Both are right around A55 performance, and 30% faster than A53.
On real-world tasks such as building software (e.g. Linux kernel, gcc) all 8 cores on a K1 working together come in slightly slower than the 4 cores on the JH7110 -- not much in it, call it the same. If you use `-j4` then it's miles slower.
I'm pretty sure that's down to the smaller caches. Or possibly TLB misses. U74 has 40-entry L1 Data and Instruction TLBs, and a direct-mapped 512-entry L2 TLB -- bigger than A53, smaller than A55. I haven't seen any information on the X60 core's TLB structure.
Half the problem with orange pi is lack of main Linux distribution support.
Haven't tried it on mine recently so no clue if it's better now.
I have a pair of Orange Pi 5Bs and they didn't really replaced my old Raspberries after spending more time on it than what I was initially willing to spend on my upgrade.
What I want is for the SoC vendors to actually learn how to participate in the kernel process. Design their drivers from the ground up to be maintainable and mainlineable.
The problem with "wanting things to work now" that we've seen over and over and over in the ARM SoC world is that each family of chips ends up with its own fork of the kernel which never gets mainlined because of one or more of the following:
* It can't actually be compiled as provided
* Successful compilation depends heavily on the build environment which is undocumented
* It depends on binary drivers
* It is written in ways that do not meet the standards of the kernel
* It modifies kernel interfaces in ways that break other drivers
* It's just bad code in general.
When this happens the vendor might update it a couple of times over the product's profitable life but inevitably they will stop doing so. If there's enough of a community around the platform and they're lucky enough to have complete source it's sometimes possible for the community to take over development of the fork and try to port the vendor code to newer kernels while slowly cleaning it up. Most of the time though there's a binary driver somewhere critical to many if not all users which will only work with a certain range of kernel versions, at which point the community is left supporting an obsolete kernel and mostly just backporting relevant fixes rather than gaining anything new. Sometimes there's a way to shim an old driver to work with a new kernel, and sometimes a driver for a newer piece of hardware from the same vendor can be made to work on the older versions, but in neither case can it be counted on.
The worst part IMO is that it's usually not even a LTS kernel that these vendors decide to settle on, it's all too often one that was obsolete and unsupported before the SoC was ever in the public's hands. If you're going to launch a Linux-based product with no intent of mainlining the kernel code at least make it run either the latest LTS or SLTS kernel.
It doesn't take years to get code mainlined, lots of vendors are doing it every day for hardware that hasn't even been released yet. A lot of SoC vendors either just don't care or actively don't want to.
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thx for any insights..
It seems to be the same one as the BananaPi BPI-F3, see: https://www.reddit.com/r/RISCV/comments/1j6c6xz/orange_pi_rv...
The link you posted goes to the exact same board as in the article.
> It's a cheaper Spacemit K1.
> The CPU spec from dtb:
> compatible = "ky,x60", "riscv"; model = "Ky(R) X60"; riscv,isa = "rv64imafdcv"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihintpause", "zihpm", "zfh", "zfhmin", "zba", "zbb", "zbc", "zbs", "zkt", "zvfh", "zvfhmin", "zvkt", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> It also have a ARM China Linlon v5 VPU and Imagination IMG GPU. The PMIC and UART is same as K1.
> And the ubuntu image from orangepi just use the same BSP kernel/uboot/opensbi from Spacemit's linux-bianbu.
EDIT: okay, looks like the official documentation lists it, but many places I looked didn't. Maybe it wasn't being detected in cpuinfo?
We're still very early in the RISC V ecosystem, so most of the processors in production pre-date current standardizations, which requires applications to target specific silicon. To add insult to injury, those individual processors are relatively new, so the dedicated image processing and vector/tensor hardware doesn't have much support yet.
Yes, I'm currently using it to successfully test vector instructions. A blog post is being written, but may take a week or so.
Keep an eye on blog.habets.se, or ping me here on HN in about a week.
Is there such a thing as a (cheap) SBC that runs RISC-V, which has good documentation (books, forums, whatever) on getting started programming on it? I'd like to get into assembly more, and hardware, and I'm interested in RISC-V for its open nature, but it can feel overwhelming getting the foot in the door.
Or is this it, and I'm just being overwhelmed by all the talk? Where would I go to get clear documentation on programming and experimenting with an Orange Pi RV2, if I went that route?
And what will Qemu emulate ? A nonexisting processor ? /s
Is the hardware open and simple enough I can reasonably run a custom assembly written mini-kernel?
The Bouffalo Labs BL808 and Sophgo SG2000 series are both asymmetric multiprocessor SoCs that allow you to run a full OS, such as Linux, on one core, and run bare metal on the other. Unlike symmetric multiprocessing, you aren't just running a premptable thread on a spare core, but you get full control of the core, with direct GPIO access and a mailbox for messaging the OS core.
You can set up a development environment in Linux, on the faster core, and compile and run your application on the smaller core, for really fast development and debugging.
Check out the Ox64 and Oz64 boards from Pine64 or the Duo series from Milk-V, for cheap breakout boards using those processors.
I may go first with some code extraction and customization from linux, before probably ending with a lot of "hand compiled" linux code.
And yes, lower-power for the moment, since I would first use that for self-hosting.
Here's an English datasheet for the SG2000 series: https://github.com/sophgo/sophgo-doc/releases/download/sg200...
…and for the C906 core itself: https://occ-intl-prod.oss-ap-southeast-1.aliyuncs.com/resour...
EDIT ---
It seems the SG200X includes an ARM block and this is a definitive nono for me. I want to buy a SOC free from ARM royalties. I tolerate HDMI/mpeg royalties though.
That said, I have to point the fact, those patents are only valid in some countries, namely subject to royalties (USA, UK, Japan... but not EU for instance).
I don't know why raspberry is not selling some of their SOCs with the ARM blocks hard disabled at sell time, namely they did not pay for the ARM royalties.
In the end, it is near impossible to buy all those RISC-V boards in my country with a noscript/basic (x)html browser, and if possible with wallet codes (or bank swift) instead of a credit card.
It's cool to see RISC-V, but I'd go with a different company.
One solution would be to always boot from the SD card and either have it partitioned to provide the SD storage that you want, or use the eMMC etc to provide the storage.