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A few sq mm at 40 nm is about $20k, and you can only configure it once. I think the Versal also gives you more useful gates at that size (thanks to block RAMs and hard multipliers).

What about power consumption?

The FPGA will have higher static power (running all the overheads) but probably lower dynamic power for the same design. 40 nm is old at this point for high-performance chips.

The static power might also depend on whether the FPGA is an SRAM type or a floating-gate type, I'd think. Does Lattice have any parts fabbed in relatively new processes?

You're right. Pretty much everything is SRAM now, though. Even the MAX 10 is an SRAM FPGA with a flash-backed storage memory.

That price is probably $4600 for one Xilinx Versal.

For the MPW run you would get ~100 parts. When everything is said and done, and you pay for packaging etc., on a MPW run you'll likely pay something like $50K. So ~$500ea

The eFabless price of $10K for a full run, including a packaged part, was an unparalleled deal.

https://www.digikey.de/en/product-highlight/e/efinix/titaniu...

Ok it's 14nm. Who cares.

This is a single chip. At scale, the ASIC is absolutely cheaper.