Imec demonstrates electrical yield for 20nm lines High NA EUV single patterning | Hacker News Reader

Imec demonstrates electrical yield for 20nm lines High NA EUV single patterning

imec-int.com

31 pointspieterr13 comments

Aha, so "2nm" really means 20nm. Good to know.

Generally the x um or y nm of a process refers to transistor dimensions (typically gate length), not metal. Minimum metal pitch is still a key dimension for the ability to build useful structures though, so advances like these are very useful.

No, the gate length on most 5nm nodes is like 40nm or something. Since around 2008-ish, the “process name” and the size of any feature have rapidly diverged (even if you use some weird pointless metric like the size of a FinFET fin, nothing on 5nm measures 5nm).

Ironically, prior to 2008 the process name was backwards the other way, for example 130nm process usually has something like 70nm gates.

It’s always really just been a marketing thing anyway, since the possible density of a given logic unit in a given manufacturers process will differ due to a huge number of factors.

Just to reiterate: in old-skool HS electricity terms, a transistor is going to need enough electrons. That number is pretty large, and is tied pretty strongly to materials and geometry. Those two things (materials & geometry) change far slower than Moore's law. What changes quickly is gate density and design cleverness.

"2nm node" means "one technology iteration after 4nm". (Well, actually after 3nm, but let's not get even more into that nonsense)

These numbers stopped having anything to do with the sizes of things a long time ago.

It might be funny to use this as a software versioning scheme. ("What do you mean the next version after v3 is 20A?")

Dividing by the square root of two with each iteration isn't any weirder than how Knuth does software versions.

But Knuth's shtick converges to a known quantity ... let me rephrase that, non-zero quantity ...

Reminds me of:

https://www.reddit.com/r/LaTeX/comments/etiuh4/just_noticed_...

So is there any objective way to compare one company’s claims or capabilities against another?

Here is an amazing discussion of that problem and a description of several metrics that answer your question: https://spectrum.ieee.org/amp/a-better-way-to-measure-progre...

The sram density is a pretty good equivalent. You can arguably do the average of sram and some logic.

If you take the square root of that...you pretty much end up with (modulo a linear scale) the existing nodes.

That gets you size. You then need power and speed, which are a bit trickier to compare without a standard/reference device.

There's no tie to what those terms mean and the actual engineering of the chips.

The "2nm node" is a marketing term to indicate its placement relative to previous iterations and competitors.

The reality is that process nodes are complicated and capturing it with a single number would be a bad idea. You could go for raw transistor density which would be better but it misses a lot of the nuances in design.

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