Proper decoupling capacitor practices, and why you should leave 100nF behind

Apparently most EE's don't do this.. I've seen decoupling caps in designs that basically do nothing.

I'm now very careful to pick ceramic capacitors with enough headroom on their rated voltage as you lose a lot if you're close to the rated value. This curve is dependent on the different ceramic types as well (C0G, X7R, etc). Cheaper ceramics have a steeper rolloff.

For personal projects I am very careful to pick higher quality ceramics (X7R if I can) and use caps rated to 2-3x my operating voltage. Likely overkill, but I'm not optimizing for cost at volume.

[0] https://resources.altium.com/p/voltage-derating-ceramic-capa...

In particular adding capacitance in random places or seat-of-the-pants-ing a layout is not helpful.

"If you have a lot of devices powered off a single rail, placing lots of high-value decoupling capacitors will add up, so pay attention to inrush current. If you’re sticking 10uF decoupling caps on 20 devices then that’s 200uF. Maybe dial it back a smidge."

The article does get it right that you need to reduce the parasitic elements to the chip, but you have to consider like, everything - not just the wires to the package, but also the lead frame, bond wires, the wiring in the chip. Usually the chip designers modeled that all out and they put decoupling capacitors on chip and did PCB model simulations that includes some specific assumption about the impedance curves of the off-chip caps, and they probably used 0.1uF in their simulations.

If anything, you need closely placed decaps to prop up higher frequencies, not lower frequencies. Remember if you have a SPI bus clocking at 25MHz, 25MHz is just the fundamental - you have the whole fourier series going up to 100's of MHz on the edge.

The answer I had always seen looking at the chip models is that there is an off-chip capacitance value below which it does not make sense to use because the bond wires effectively isolate the chip above certain frequencies (i.e., while smaller value capacitors have higher SRF it doesn't matter because the chip can't "see" the capacitor due to the bond wires screening it out).

If you knew where that roll-off was, and you knew the curve of your capacitors + board parasitics, you'd place a cap as close as you can to the chip in the frequency band right below the roll off of the bond wires to prop up that zone. Then, you'd place larger caps farther away because, as the article notes, the inductance goes up but also you're just looking to prop up the higher impedance-at-lower-frequencies curve of the tiny cap that's close to the chip.

So a lot of it depends on the exact chip you're working with and how well designed it is. A classic chip design team would have an expert who did all the parasitic modeling of the package, board, and then they'd do a noise analysis on the chip and recommend a minimum on-chip decap so the board designers don't have to worry too much, they can get away with "almost anything" in the 0.1uF range. Unfortunately chip design teams are getting leaner and leaner these days and I don't see the same level of care being put into chips. I think we more or less get away with it because there is so much margin in the chip timing; also modern chips are "mostly" (>50%) fill cells -- e.g. decoupling capacitors -- that are placed right up against the logic gates so you can get away with bloody murder on the package and power distribution networks (background: modern chips are wiring-limited, not transistor-limited, but for process stability reasons you still need to make transistors everywhere at a uniform density, so they instantiate dummy transistors that are wired as capacitors between power and ground).

Where it really starts to matter is if you had e.g. a PLL and you're trying to reduce noise that the loop filter can't get rid of and in those cases often times you need much smaller capacitors because they have much better performance at higher frequencies. Yes, they suck at low frequencies - but your noise problem isn't in the 1MHz band anyways; the loop filter can track that out. It's going to be in the 100MHz+ range.

And as someone noted elsewhere, in-rush current is a real problem, and too much capacitance can cause a problem for regulator stability; especially the extremely high performance ceramics. And, if you're doing an extremely power efficient design you may need to consider factors like leakage and losses due to CV-energy cycling if you shut down significant portions of the design when not in use.

(edits for clarity)

USB-C sorta solves this because it starts at 5 V and steps up after being plugged in, but then you have issues with arcing on unplugging (see: USB-C connector spec, one of the last appendices deals with this).

> 1. If you have a lot of devices powered off a single rail, placing lots of high-value decoupling capacitors will add up, so pay attention to inrush current. If you’re sticking 10uF decoupling caps on 20 devices then that’s 200uF. Maybe dial it back a smidge.

The conclusion of the article specifically mentions inrush concerns as one of the reasons to use large values. For the notch itself, relying on the difference between 0.05 Ohm and 0.02 Ohm decoupling is gonna make for a bad time, especially given how much that notch will move across DC bias and temperature.

Extreme parts cost a whole lot more

Screenshot: https://i.imgur.com/sMaXBpN.png

If you really need to be on the lowest column (highest capacitance) for a given voltage rating, you'll either pay for it in voltage derating, temperature performance, tolerance accuracy, package height, or just pay for it in literal cash.

You cannot go below the lowest column, they have not figured out how to build a 10uF/25V/X7R/0603 MLCC, that is just not a thing you can buy.

With a given dielectric, material properties science only go so far. You're leaving performance on the table if you select a given package size with less capacitance and a lower voltage rating than what's available. (Assuming decoupling, not analog stuff where you need exactly 438.6 pF for a particular resonant frequency or something). Each package size has basically a constant inductance, and usually, capacitor height isn't that critical - you don't want to be oversquare, but they don't sell many of those. Each manufacturer publishes a waterfall diagram, but all manufacturers are working with the same physics.

Conversely, if you've selected an X7R dielectric and an 0603 package for a decoupling capacitor, there's not a great reason to go with a 0.1uF value, or to restrict yourself to 6.3V rating - eg [2]. They make a 0.47 uF 25V capacitor that's otherwise identical! [3] And because designers are lazy and default to 100nF, the part with 1/5th the performance is literally 6% more expensive!

Note that for 0402 packages, the 100nF capacitor is typically the right part to select! You can't get a 120nF/X7R/0402 at any voltage rating above 6.3V, the 220nF and 470nF are exotic parts that sacrifice stability and accuracy for maximum capacitance in a volume, but a 100nF/16V/X7R/0402 is a pretty good default.

[1] https://content.kemet.com/datasheets/KEM_C1002_X7R_SMD.pdf

[2] https://www.digikey.com/en/products/detail/kemet/C0603C104K9...

[3] https://www.digikey.com/en/products/detail/kemet/C0603C474K4...

Switching regulator frequencies have become much higher since the 80s. It's common to have switching regulators operating in the MHz range with small ceramic output capacitors and relatively low value inductors.

No, they aren't. LCSC is a very reputable distributor that has lower margins by having much cheaper labor and having absolutely insane economies of scale.

The main reason MLCC are so popular... is the price. =3

Every production board will have capacitors in other places, so removing one of them at the expense of increasing chip size and PCB area isn't a good trade.

For high density designs with high budgets, you can embed capacitors and other passives directly into the circuit board in cutouts. You can also use special capacitance layer substrates to form a big distributed capacitor between two copper planes in the PCB.

There are a lot of options out there, it just doesn't make sense in most cases because putting a capacitor that costs less than $0.01 around the chip is trivial.

The basic answer is basically what the original article says. If you don't want the mental burden of figuring it out, the spec gives you safe defaults that should work for almost all uses. But it's almost never the case that you need to do it that way.

Seems to be targeted at a different audience than the article.