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Comment by whatshisface | Hacker News Reader

Leakage current is what heats up the chip, and if it drops by five orders of magnitude when it's cool, the energy requirements for refrigeration will be low. Memory chips are already not that power-dense (on the order of 10W for a DIMM) so we're only talking about extracting 1mW of heat from the cryo chamber.

>As IOFF at 77 and 10 K decreases by four to five orders [29], the primary constraint of building a large memory array, i.e., leakage current (Ileak), will not be a major concern and will lead to novel design tradeoffs for memory optimization.

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This comment assumes that the leakage current is all of the power draw, and not just the majority of it. I find it unthinkable that leakage current is 99.99% of the power draw of SRAM. 95% sounds believable, but then you're talking about removing 500 mW, not 1 mW.

This also gets rather tricky, because the standard way to connect computer chips is with copper traces, which are wildly good conductors of heat. A solution like this will probably need optical interconnects with the made from a thermal insulator.

It's a fun design problem to chew on

> Leakage current is what heats up the chip

Leakage current is generally a rounding error for heat. In CMOS, the power that causes the most heat is the dynamic switching power which is lost to P = C * Vdd^2 * frequency

Which implies that for the fastest chips, most power is lost simply to running the clock which has both the highest frequency and largest capacitive load.

Where leakage current matters is for battery driven systems where you spend most of your time sleeping.

I strongly suggest that you go over this lecture "CMOS Power Consumption": https://course.ece.cmu.edu/~ece322/LECTURES/Lecture13/Lectur...

But in a large SRAM, most of the gates are not switching, at any given time. The cells are mostly just sitting there holding their data.

And if cooling it lets you shrink the SRAMs that’s also going to let you reduce the capacitance, so switching power will also be reduced. I’m sure a design optimised for low temp will do some clever stuff with clock hating as well.

The problem here is that you generally put SRAM on the same die, or at least package, as the processors. And those do switch many of their gates.

So you’d probably have to do this in a case where you want a lot of fast RAM in a different box, with some really fast optical interconnect to your processing cores.

The sense lines, however, are switching--as is the clock. Just because the RAM cells are sitting there doing nothing doesn't mean that everything else in the RAM is also idle.

Also, take a look at the Apple M3 chip, for example. Note how much of the die size isn't RAM.

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