Gate-level simulation of ASIC in browser | Hacker News Reader

Gate-level simulation of ASIC in browser

znah.net

221 pointspicture31 comments

I'm amazed. The technical wizardry involved in stuffing this into such a small area of Silicon, then simulating it in a web browser, is awe inspiring.

At the same time I'm filled with doubt I can get my BitGrid to the same state.

You can do it too, come on over to https://www.tinytapeout.com/

I _need_ to tinytapout! Don't know what, don't know how, but the sense of need is tickling! I feel like twelve again in front of a 286 without a case.

Interesting: https://www.tinytapeout.com/competitions/demoscene-tt10/

This seems to be the currently open tapeout.

How low-level can you go with tinytapeout? One can imagine the insanity of doing a manual layout to push a demo to extremes.

You can work at the polygon level if you really want to, you can write gates and have it lay them out for you (or place them yourself), or work in a higher level language like verilog and have it compile them into gates for you (what most people do) - your choice

How good are things like verilog at producing efficient layouts?

Coming from the perspective of software. Hand coded asm can usually squeeze a lot more than a compiler into a small number of bytes, but that's mostly due to compilers targeting speed of execution instead of size.

Verilog describes the logic. This is extremely simplified, but you can imagine that verilog and other HDLs are "compiled" into a big schematic of logic gates and a big list of signal timing constraints between them. From that schematic and constraint list, a solver then works to do place and route.

Both of these intermediate stages between verilog and the final working hardware are where all of the secret sauce in semiconductor design actually lives. Both of these steps will be affected by the process target. Are you building for an FPGA or CPLD? Which one? If for an ASIC what is the process node? What logic elements are available in your node? Just like when you order a PCB, the process design rules generally come with prescribed information about the manufacturing constraints -- what works and what doesn't. And ultimately you cant rely on hand layout to throw down millions/billions of circuit elements anyway so you have to build solvers and all kinds of other mind bogglingly sophisticated automation to the party.

The diminishing returns of manual optimization here should be evident; if you want to do that work, become a process design engineer.

We do need more open information in this space! Tiny Tapeout is such a great project!

That's all very analogous to software compilers, but doesn't really answer the question I had.

Specifically for Tiny Tapeout, how much is there to be gained by going low level? I feel like using a subset of verilog features might get you most of the way there.

Consider that there is a 512 byte BASIC interpreter in asm, that's well beyond what a compiler could manage. I would expect logic expressions in verilog to get closer to a hand crafted approach than that, but I might be wrong.

Can be huge depending how low level you are allowed to go. For example from recent

38C3 - The Design Decisions behind the first Open-Everything FABulous FPGA https://www.youtube.com/watch?v=3Lll9_-gYGg

there was a mention of using open source SRAM library versus Siemens one. Open source macros build 1KB 12MHz ram while siemens is 3x capacity 100MHz

https://youtu.be/3Lll9_-gYGg?feature=shared&t=1740

Siemens delivers this by breaking foundry design rules :)

https://youtu.be/3Lll9_-gYGg?feature=shared&t=1878

(I've written Verilog compilers, normal compilers, designed gates and chips, can read polygons, written assembler, etc etc)

I think it is all very analogous to software compilers, but IMHO writing in assembler is an order of magnitude easier than manually laying gates, and maybe 2-3 orders more than manually laying polygons.

Yes you can get better performance and density by laying polygons, especially stuff like ROMs and RAMs and regular ALU structures, but it's a lot of work and not a rathole you want to go down as a beginner

How about if I'm a masochist :)

I do have form when it comes to the needlessly complicatedly making things small like impenetrable programs that fit in a url https://c50.fingswotidun.com/show/?code=z1s-xy*dee%2B%2B2*z!...

Polygon level seems more akin to machine code than asm. That is (usually) a step too far for me.

Very tempted to do something for tiny_tapeout, it does seem the kind of nerd sniping aimed at me.

I'm going to take a stab and say judging from your username, you are vaguely near me (Chch).

If we're talking nerd sniping: A polygon layout for an analog computer that directly generates the RGB analog VGA signals. :-)

(Must resist...)

Mostly I'm just trying to explain just how (relatively) hard things are, so people wont get too far out of their depth. I'd really recommend doing the usual HLL/assembler approach - start with a verilog only implementation, build a test bench (tiny tapeout has infrastructure for this), look at the bits you want to be faster/denser, try a hand compiled gates implementation (you can do this within verilog for a start), then maybe even hand lay it out

Yes, I live south of you in Dunedin, though I worked in the SF Bay Area for a couple of decades doing all sorts of stuff including chips, OS's, embedded crypto stuff etc

If you want to do low level design, you can look at the Micro Magic public domain tool set. As someone said above, Verilog only describes the logical function (ranging from the RTL level to the gate level.) You'd need other tools to work on everything physical, like placement and routing.

https://github.com/yarpose/YARPOSE.Micromagic_PD

Those baseball caps are BALLIN

Author here, and this is how running your design on real hardware feels https://x.com/zzznah/status/1876684831222067350?t=b8-zl-h6uV...

See also virtual 6502 and ARM1 e.g. http://www.visual6502.org/sim/varm/armgl.html

You might also want floooh's remix which has a nicer UI, with the ability to see instructions evaluated, modify memory, assemble/disassemble code, view traces, etc.

Visual 6502 remix: https://floooh.github.io/visual6502remix/ Visual Z80 remix: https://floooh.github.io/visualz80remix/

This is going to sound quaint, but because of this simulation, this is the first time I realized they're _literal_ flags on the sides of the CPU, which is blowing my mind.

You mean the pads? Those are the connection points for the wires that connect to the external package pins.

Unless they are hooked directly to little Swiss clock figurines holding semaphores. At that point you’d kinda have the amazing human CPU from Three Body Problem.

How many gates are here?

Is it near the crossover of where the same amount of logic can implement a tiny CPU which can run a program to generate the same output?

(I guess not in this case, because it needs to output 18 million pixels per second, and a micro-CPU probably won't be doing that anytime soon)

This is amazing, I assume the sections lighting on/off are getting electrically activated, but what is this yellow orb slowly moving from left to right near the top?

My hunch is that that's the pixel that's currently addressed?

Looks like it - if you turn the simulation speed slider way up you can see the image forming as it passes over.

It's the position of the electron beam in a CRT monitor -- from the VGA signal the hardware is emitting.

Yep, that's what I meant

Completely wild to me that you are backing out the netlist from the geometry gds.

First I implemented it, and then learned that it is called Layout vs Schematic (LVS). For now automatic conversion is limited to stateless cells, but I'm planning to rewrite the circuit extractor to support all flipflops and latches.

It looks visually cool

Tyrell Corporation

Reply on news.ycombinator.com