Why we invested in Silicon Box and the advanced chiplet packaging
medium.com
medium.com
> Reduced Power Consumption: The smaller size of individual chiplets contributes to lower power consumption. Each chiplet can be optimized for energy efficiency, and the overall system can be designed to minimize power waste. This feature is particularly crucial as the demand for energy-efficient technology grows in sectors like mobile computing and data centers.
Each chiplet can be designed to minimize power consumption? Of course, sure, anything can be designed to minimize power consumption. The overall system can be designed to minimize power waste? Sure, I guess. But do the chiplets actually help there? If they are saying chiplets help there—I don’t see it. If they are saying they can work around it and it doesn’t hurt as much as you’d expect, I believe them.
Overall I’d expect chiplets to have slightly higher power consumption than a similar monolithic chip. The network isn’t free. There’s some loss of flexibility as the design has to be broken up over multiple chips.
But I’d also expect the higher yields should let them use newer process nodes, so in the end… the choice of a similar monolithic chip is probably not available!
Also I guess they could do better power gating than a monolithic design probably.
And I suppose that having all heat sources right next/on top of each other forces you to spend design effort to lower power consumption ;)
I've worked on the "MCM or monolithic" decision making process and the only way MCM ends up lower power is if it lets you optimize the silicon-process selection of the different chiplets and the savings from _that_ outweighs the power cost of the die-to-die IO.
OP is right - "reduced power consumption" is not an automatic benefit of chiplets. it only happens in select circumstances, which are (a) low enough bandwidth interface between the chiplets that the extra IO power cost isn't too onerous and (b) chiplets allow you to move enough of the logic to a better process node than you could use for a monolithic chip (why not move the whole monolithic chip to the better node? because you've got some critical function that is 'stuck' at an old node) to more than offset the power cost.
It was a throw-away at the end there. I’d assume a whole chiplet could have its power cut completely. But I don’t know if anybody actually does that.
like a lot of stuff, the full answer is "it depends", but mostly - no. Chiplets and monolithic ICs get about the same power gating quality/efficiency (whatever your metric is).
>I’d assume a whole chiplet could have its power cut completely.
You _could_ do this - put a chiplet on an isolated power plane in the package and then cut the power to the entire chiplet. But that is IMO rare because (a) you've just moved the problem somewhere else - the power gates now need to appear on your board, not on the PCB - and (b) frequently you don't want to completely cut the power to a whole chiplet..
For instance you may want to keep some data resident in internal memory as the (power/time) cost of re-writing that data after a "full" power down may exceed the extra power saved between the full/partial power down. You'll end up doing a pretty tedious analysis of how long does it take to initialize the chiplet and how long is it likely to be powered down vs. the different power consumption in the different modes.
Anyway, on chip power gating is very good - you really can turn the power off 100% in the gated region - at the cost of extra silicon area for an isolation band around the gated region and level shift/isolation cells for all the I/O into/out-of the gated region - all of which you also have to do in the "power down the whole chiplet" approach.