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Comment by alecco | Hacker News Reader

> Each version is severely memory bandwidth bottlenecked, the CUDA version suffers the most with its practical 11.8 GB/s device-to-host bandwidth due to its PCI-Express 3.0 x16 interface.

PCIe 3.0? What?

https://cowfreedom.de/#appendix/computer_specs/

> GeForce GTX 1050 Ti with Max-Q Design (PCIe 3.0 x16) (2016)

> Intel Core i5-8300H (2020)

This is a low-price 8 year old GPU and a 4 year old CPU. And he seems to be including loading the data to GPU. Newer cards have wide PCIe 5.0 or some faster interconnect, like Nvidia Grace-Hopper.

Also he is comparing his own CUDA implementation. He should use one of the many available in CUBLAS/CUTLASS. Making a good CUDA GEMM is a very difficult art and very hardware specific

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> Newer cards have wide PCIe 5.0 or some faster interconnect, like Nvidia Grace-Hopper.

There aren't any (edit: consumer) GPUs with PCIe5 yet, though they probably aren't far off. Plenty already have PCIe4 though.

Consumer cards are PCIe 4.0 x16. H100 PCIe version is PCIe 5.0 https://en.wikipedia.org/wiki/Hopper_(microarchitecture). And it's been out 2 years already.

So everyone is supposed to do all of their testing on H100's?

4090 (2022) PCIe 4.0 x16 is quite decent. The major limit is memory, not bandwidth. And 3090 (2020) is also PCIe 4.0 x16, and used cards are a bargain. You can hook them up with Nvlink.

Nvidia is withholding new releases but the current hardware has more legs with new matrix implementations. Like FlashAttention doing some significant improvement every 6 months.

Nvidia could make consumer chips with combined CPU-GPU. I guess they are too busy making money with the big cloud. Maybe somebody will pick up. Apple is already doing something like it even on laptops.

get a GH100 on lambda and behold you have 900GB/s between CPU memory and GPU, and forget PCIe.

Where are you seeing 900 GB/s?

The 900 GB/s are a figure often cited for Hopper based SXM boards, it's the aggregate of 18 NVLink connections. So it's more of a many-to-many GPU-to-GPU bandwidth figure.

https://www.datacenterknowledge.com/data-center-hardware/nvi...

this is bidirectional bw and it's gh200, not gh100

That doesn't add up, because you're now exceeding the memory bandwidth of the memory controller. I.e. it would be faster to do everything, including the CPU only algorithms, in far away VRAM.

latency might be higher and latency usually dominates CPU side algorithms.

TIL, I missed Hopper already having it. I assume the RTX 5000 series will bring it to consumers.

For the consumer GPUs, PCIe 4.0 x16 has plenty of BW headroom. The full sized x16 is more for stability reasons. Some vendors even put a couple of M.2 slots on PCI4/5 GPU board to recuperate the unused PCIe lanes.

That's mixing apples with oranges.

Some low-end or middle range GPUs really only use 8 lanes, because that's how the chip is designed. Fewer lanes -> less silicon area for the pcie logic needed -> cheaper.

The chips which use 16 lanes take advantage of it and can saturate the link.

Smaller GPU silicon is also often designed more around the laptop market, where it's common for the CPU to not have more than 8 lanes available for the GPU.

what does a laptop GPU have to do with a server grade xeon that the article is comparing against?

Well let me tell you about the pretty high-end and expensive L40 that shipped with PCIe-4.0 to my utter dismay and disgust. Only the H100 had 5.0 although I could already saturate 4.0 (and 5.0) with Mellanox NICs and GPU/StorageDirect. Waiting for the next one to maybe get 5.0.

Supposedly the Intel B580 releasing friday will use PCIe 5.0 8x.

PCIe 4.0 16x

https://www.intel.com/content/www/us/en/products/sku/227961/...

That's A580. Correct link https://www.intel.com/content/www/us/en/products/sku/241598/...

"PCI Express 4.0 x8"

So Intel is doing the same artificial performance limitation. Nvidia 4060s are also PCIe 4.0 with half lanes (x8). Argh.

Alternatively, at that performance level it doesn't make a difference, so better to save the $5....

that's not true, H100 NVL is PCIe gen5 x16.

The CPU was launched in Q2 2018, so that is also 6 years. I wonder what the outcome will be with a CPU that supports AVX-512 and a more recent GPU.

GH100 can do 900GB/s HtoD.

And both 3090 and 4090 can do 32 GB/s host-device. Not far from CPU-RAM. You only load the matrix once. The bandwidth for the matmul is orders of magnitude larger and happens all in device and mostly in cache.

No it can’t. That’s d to d

Well, device to device is technically doubled because you have a read and a write. But yes

No. D2D is arroubd 3TB/s

no.

[root@gh200 nvbandwidth]# nvidia-smi | grep GH200

| 0 NVIDIA GH200 480GB On | 00000009:01:00.0 Off | 0 |

[root@gh200 nvbandwidth]# ./nvbandwidth | grep -E 'host_to_device_memcpy_sm|device_to_host_memcpy_sm' | grep ^SUM

SUM host_to_device_memcpy_sm 357.45

SUM device_to_host_memcpy_sm 352.05

[root@gh200 nvbandwidth]#

d2d is much higher:

[root@gh200 cuda-samples]# ./bin/sbsa/linux/release/bandwidthTest --dtod | grep -B1 32000

   Transfer Size (Bytes) Bandwidth(GB/s)
   32000000   2294.8

[root@gh200 cuda-samples]#

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