Turning Off Zen 4's Op Cache for Curiosity and Giggles | Hacker News Reader

Turning Off Zen 4's Op Cache for Curiosity and Giggles

chipsandcheese.com

68 pointsmfiguiere10 comments

>> Performance monitoring data shows increased pressure on the decoder in SMT mode across all integer workloads.

That's probably why AMD put 2 decoders in Zen5.

One thing I'd be interested in, which kind of belongs in this space:

In the last years, there were lots of performance reducing software patches for security flaws in CPUs, e.g. meltdown, specter and god knows what. Is there a way to disable those security fixes and increase performance, e.g. for servers that only ever run self written backend code and if so, is it common practice?

I feel like I wouldn't want those security fixes on that server I am running which only runs postgres, is only accessible to other servers via the postgres port and does nothing else.

Phoronix regularly tests this, search for keyword mitigations

https://www.phoronix.com/review/amd-zen5-mitigations-off

I ran mitigations=off on my Zen4 until I saw that phoronix article and realised that in most workloads it made essentially no difference, and even harmed performance in others. I no longer run mitigations=off. But on my old i7 7700HQ mitigations=off improved performance by 10-20% depending on workload.

Hmm, does this affect power draw?

I believe the opcache is too small to really matter here to disable. Even though it's fast SRAM, it's not too many transistors.

Performance loss will of course cause the task to run longer which increases total power usage.

It makes much more sense to disable SMT instead first, with the performance losses being on par most of the time, while this bringing serious powwr savings.

I would assume the inverse relationship. That enabling the op cache would reduce power draw. Though I also wouldn’t be surprised if they’re always running the decoder.

The very reason for the Loop Buffer was to let decoder power down within tight loops, so I'd assume micro op cache would have similar effect, except with more impact on performance.

Very curious as to the typical strategy for implementing low power modes on things that are highly latency sensitive like a decoder.

Like would whatever mechanism they’ve got behave well if fetches were alternating between cache hits and cache misses?

Well, the decode used to use 15% of an x86 core's power budget but it hasn't grown as fast as the other structures so I'd guess more like 10% these days. So you're losing out on being able to turn off a small but noticeable part of your active power usage. But on the other hand fewer instructions executing means less active power draw in the rest of your core too. So it's not clear which way it goes in terms of Watts, but certainly you use more Jules.

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