I nerd sniped myself with x86 Message Signaled Interrupts format

I need your help! There seems to be some historical use of bit 11 of MSI data to be defined as "Delivery Mode" just a copy of bit 2 of MSI address, which is documented for "Delivery Mode" in the Intel SDM. Why there is a copy in message data and what for? I don't know. The earliest document I could find which mentions that is ICH2-M datasheet 290687-002 see page 5-58 and 5-59. I think this seems to be documented up to ICH10. Maybe it is connected to Itanium somehow (but it does not support logical delivery?!) Sometimes there is a note that chipset clears that bit when sent to CPU. Seems like Linux kernel in x86 msi.h has "dest_mode_logical" fields for both address/data fields, but never uses that. I think I seen Windows to set it, when examining MSI data/address pairs. Oh and there is a lot of fun with RH bit and DM bit combinations which SDM is contradicting to itself - likely also due to the Itanium compatibility. Lastly, on AMD the format of MSI/address/data is undocumented, but funnily for NMI encoding, you have to use hypertransport encoding and not intel encoding to trigger NMI on AMDs. This rabbit hole is very deep! Where to document it once we know everything?