NAND Flash Targets 1k Layers | Hacker News Reader

NAND Flash Targets 1k Layers

semiengineering.com

62 pointsrbanffy10 comments

The second paragraph:

> Those additional layers will add new reliability issues a number of incremental reliability challenges, but the NAND flash industry has been steadily increasing the stack height for nearly a decade. In 2015, Toshiba announced the first 16-die stack using through-silicon vias. That enabled higher bandwidth, reduced latency, and faster I/O, while also helping to pave the way for stacking of other types of memory and logic chips.

Stacking multiple dies (with or without TSVs) is an entirely different kind of stacking from building multiple layers of memory cells on a single die, which is what 3D NAND is all about. Samsung was the first to deliver 3D NAND, and IIRC Toshiba was tied for fourth to reach that milestone.

>export rules restrict stacks of more than 128 layers. So countries subject to those restrictions get an end-around by simply stacking 128-layer modules

I'm interested in the story behind this.

https://www.bis.doc.gov/index.php/documents/about-bis/newsro...

Specifically, https://www.federalregister.gov/documents/2022/10/13/2022-21...

I find 128 layers of components on a die already mindblowing.

The article hints at the ability to make multiple layers with a single lithography step. That seems incorrect based upon my mental model of how semiconductors are typically manufactured. I’d expect a lithography process for every layer. Which one is correct?

3D NAND is built by depositing dozens of alternating layers, then etching tall, narrow vertical channels down through the stack. Those channels are filled in with other materials to form vertical strings of memory cells. The ability to make many layers of memory cells without needing lithography and etch per layer is the main reason why 3D NAND is so cost-effective and able to continue scaling in density far beyond what was achievable with planar NAND flash memory (which could only improve by making memory cells smaller, but they were getting too small to actually work).

Intel's 3D XPoint memory (used in Optane products) was doomed in part by the fact that it did need lithography for every single layer, so it couldn't scale up in layer count cheaply.

Know of any YouTube videos which animate the processes?

This one is already 4 years old, but actually describes the operations https://www.youtube.com/watch?v=PdS3jkDKmOU

> lithography process for every layer

It's not. They are similar process steps, deposition, etching, etc but they are applied at once to long deep holes and other staircases that intersect the many layers. The layer is an insulator or conductor (etc) which intersects an entire plane of these tubes. Equals one planar wire which addresses one whole plane of tube intersections.

So that's one of the problems in there: similar operations but applied in grossly different circumstances, but lots of unknowns and different ideas being thrown at the wall. And that's one of the opportunities: it's hard to tell how long this will work. Like, how many years of scaling this will produce.

Reply on news.ycombinator.com