Antenna Diodes in the Pentium Processor
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I'm a physical design engineer that uses software from Cadence and Synopsys to do chip layout of blocks with billions of standard cells. Our flow automatically puts antenna diodes in for all block input pins. Then the tools are usually good enough to breakup internal nets with layer jumping to avoid antennas.
Some of the charge also comes from the CMP process. Modern chips have about 20 layers of metal but there are lots of other via layers in between those and then all the base layers with the actual transistors. You want the wafer to be flat before building the next layer.
It’s precisely these orthogonal, secondary concerns that make every industry more difficult than people on the outside might think.
Articles like yours shed light on these challenges.
I’m reminded of a recent project working on a (small!) data warehouse where for the first time in my career I had to not only be concerned with theoretical performance of queries, such as the presence or absences of indexes, but orthogonal concerns such as the time taken to rewrite terabytes of data on disk during night ETL jobs… combining with the “change rate” of the source data.
Your article is a similar concern that only specialists in the in the industry are even aware of: it’s not enough to logically route connections — a challenging optimisation all by itself — but there are these competing physical optimisation issues as well that need to be simultaneously optimised!
Chips seem to be around 25mm sq, and the smallest features around 10nm. If you scaled up so the smallest feature is one mm then the chip would be around 2.5km square. (over 1.5 miles on each side)
If the smallest feature was about the width of human hair then divide the above by 100.
Instead of a hedge maze maybe we can have VR "walking through a 8086 or 8088" chip style maze in the future.
However, second question, does any chip actually use these for anything afterward? Or are these ever built so they actually do something other than simple provide manufacturing protection?
Example, they build up charge. So then the charge build up itself is effectively used as some form of remote communication method or channel between various portions of the chip. The diode discharges and in discharging effectively acts as some form of communication transfer.
Others, or it serves multiple purposes. One during manufacturing, one after manufacturing? Safety mechanism during manufacturing, and then the charge buildup location is oscillated, purposely charged, or used as a charge outlet for some other reason?
Others, Light Emitting Diode is, kind of by the name, a diode. Any of these that basically do blinking communication or something similar? Emits light when the charge breaks down, then that is picked up and used as data transfer?
Others, not going into extensively. Tune radio and TV receivers (varactor diodes). Generate radio-frequency oscillations (like actual antennas) (tunnel diodes, Gunn diodes, IMPATT diodes).
Basically, anything other than a safety mechanism for manufacturing?
> Note that when the chip is completed, every transistor gate is connected to another transistor's source or drain (which provides the signal to the gate)
That's a very curious assertion, which made me think a bit more (it feels incorrect at first but on a second thought it looks correct)
I would think of "pure input pins" but I suppose those have pull-up or pull-down "resistors" which in silicon are actually diodes? gateless fets?
(If not, why not?)
Later technologies (28 nm and below) have extensive design rules around prevention of "antenna" effects.
The vast majority of people have little idea of how much intellectual effort has gone into the current state of technology.
What’s weird is asking the question and just nope-ing out of the resulting conversation.
I hopped onto the Moore's law bus during the 180-nm to 130-nm transition. I hopped back off during the 65 to 45-nm transition, and I'm glad I did. I can't even imagine what EDA tools have to deal with now.
In school, your programming exercises are well-defined, small, and can be completed in a few days. First day of my internship with Intel: "Here is a 50,000-line program somebody has been working on for 8 months. But it's too slow, we need to you speed it up by 10x before the summer ends." LMAO. But I figured out how to do even better than that. The routing graph was implemented using pointers from one node to another. But the grid was rectilinear and not very sparse so I could just use a 2d-array to store the graph. Improved memory, improved cache utilization--it ran 2,000 times faster :-) I got a divisional award and so many stock options I was able to buy a house and a brand-new porsche 911 a few years later.
Imagine your job is to solve an NP-hard problem. Like placing the cells on a chip, or routing the chip. The runtime grows exponentially with your problem size....
...and your problem size doubles every two years :-) Every two years, all your data structures, all your algorithms, have to be revamped so that they can handle twice as much data. We used to call it "Even More's Law" :-)
As far as what tools we used, back then Intel mostly used in-house designed tools. They were not very friendly to newbs, they were built for power users. Hard to use, cryptic commands. Hyper customized to Intel's design flows. Could not be used at any other company.
Every year it became harder and harder to compete with outside vendors like Cadence and Synopsis. Eventually, the era of chip companies making their own EDA tools ended. It was fun until it ended.
The best part, though, was it was the 90's. The iron curtain had fallen, we were friends with Russia and the east block :-) Bill Clinton had eliminated the budget deficit, so borrowing costs were very low, and businesses could expand. The whole dot com thing was going on, and everybody was making more money than they could count.
Then...the supreme court puts George W in office. We spent $3 trillion on oil wars, for false reasons, and for which we got nothing in return. Sure did piss off all of our new friends like Russia, though.
Record surpluses went to record deficits. Interest rates rose, and the entire world economy just collapsed in 2008. Which was right around when this year's high-school graduates were born....nobody has seen what the economy should be like for over a generation now.
Both Synopsys and Cadence exists because of the work Alberto Sangiovanni-Vincentelli and his students at Berkeley did for Intel to enable synthesis and automatic layout of 386. He was co-founder of both :)