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Comment by JohnBooty | Hacker News Reader

From the article:

"[The E cores'] instruction set is the same as M4 P cores, ARMv9.2-A without its Scalable Vector Extension (SVE)"

I mean, not having the SVE do not make them run all the workload of P cores, and this is what I said already? They are not of course different ISAs at the core, but they're not the same cores per se. When you are missing extensions, you can't address these cores when there are these instructions present. Forcing it, would kill your application with an illegal instruction error.

So heavy computational stuff is not the target of E cores, you need P cores for that.

The quoted sentence is poorly worded. The P and E cores are fully instruction set compatible. It isn't possible to meaningfully know ahead of time if the instructions will be used on any given core, and trapping along with a migration is expensive and needless. The M4 as a whole does not support the SVE/SVE2 extensions anywhere, which is what the article is saying in the given quote.

The M4, on all cores, does support the SME extension, which includes a subset of SVE instructions at a wider vector length (512-bits), optimized for throughput. SME instructions are handled by a separate accelerator coprocessor unit attached to each cluster, shared by a number of cores, and don't "exist" in the normal instruction pipeline (where e.g. 256-bit SVE2 instructions would be handled.) This was all true of the proprietary Apple AMX extensions in previous cores as well, as far as I'm aware.

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