Which is why letting it fail and letting the investors feel the pain is a good lesson: don't invest in schemes you don't understand and don't have transparency into.
If you want to be pedantic, heeding this lesson is what got Intel into this mess in the first place. If Intel bought EULV fabs from ASML a decade ago, they theoretically could be competitive with TSMC. Intel didn't invest, citing how poorly-understood and opaque EULV was and assuming they could beat it with another process. That miracle process never materialized, and now Intel has learned that without risk you get no reward.
Intel's decision wasn't even irrational, either. EULV is poorly-understood, and competing with it would have avoided the TSMC/ASML integrated monopoly that effectively manifests today.
TSMC's 7nm where they jumped ahead of Intel used quad-patterning DUV which is also what Intel was trying. TSMC only started to introduce EUV at 6nm and 5nm which is when ASML had made great breakthroughs and vastly increased WPH. And even then EUV was only used sparingly at the most critical layers. Because other problems were still being solved like uptime and compatible pellicles.
If you want to blame Intel's decisions then look at their use of cobalt contacts or COAG use. They tried to do too much at 10nm when shrinks were getting harder.