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Comment by guerrilla | Hacker News Reader

Yeah but why don't we have like 500MB of SRAM per 8GB of RAM. Certain addresses could be faster, in the same way /dev/shm/ is faster.

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This is sort of the role that L3 cache plays already. Your proposal would be effectively an upgradable L4 cache. No idea if the economics on that are worth it vs bigger DRAM so you have less pressure on the nvme disk.

Cache is not general purpose as far as I know. I want to be able to do whatever I want with it.

Where’s the market demand for that?

Yeah, you’re basically betting that people will put a lot of effort in trying to out/optimize the hardware and perhaps to some degree the OS. Not a good bet.

When SMP first came out we had one large customer that wanted to manually handle scheduling themselves. That didn’t last long.

Effort? It's not like it's hard to map an SRAM chip to whatever address you want and expose it raw or as a block device. That's a 100 LOC kernel module.

Where is the market demand for faster RAM? This isn't a good question.

Gamers, 3D modelling professionals, IBM, HP, ORACLE, many IT departments, etc… ?

Coreboot and some other low-level stuff uses cache-as-RAM during early steps of the boot process.

There was briefly a product called vCage loading a whole secure hypervisor into cache-as-RAM, with a goal of being secure against DRAM-remanence ("cold-boot") attacks where the DIMMs are fast-chilled to slow charge leakage and removed from the target system to dump their contents. Since the whole secure perimeter was on-die in the CPU, it could use memory encryption to treat the DRAM as untrusted.

So, yeah, you can do it. It's funky.

AMD offers CPUs with over 768MiB of cache if you're willing and able to afford them.

There used to be a DRAM with build-in SRAM cache called EDRAM (Enhanced DRAM, not to be confused with eDRAM Embedded DRAM).

• 2Kbit SRAM Cache Memory for 15ns Random Reads Within a Page

• Fast 4Mbit DRAM Array for 35ns Access to Any New Page

• Write Posting Register for 15ns Random Writes and Burst Writes Within a Page (Hit or Miss)

• 256-byte Wide DRAM to SRAM Bus for 7.3 Gigabytes/Sec Cache Fill

• On-chip Cache Hit/Miss Comparators Maintain Cache Coherency on Writes

Afaik only ever manufactured by a single vendor Ramtron https://bitsavers.computerhistory.org/components/ramtron/_da... and only ever used in two products:

- Mylex DAC960 RAID controller

- Octek HIPPO DCA II 486-33 PC motherboard https://theretroweb.com/motherboards/s/octek-hippo-dca-ii-48...

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