SSDs cost half of what they did in 2011
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Can anyone provide more information on the nature of that limitation?
I did find reference to this article from 2 years ago: http://features.techworld.com/storage/3211959/is-nand-flash-...
It just seems like it's talking about the usual ongoing issue of, "we're near the cutting edge of lithography techniques", but that's kind of a given (you always build on the best lithography method that can scale, which tends to be fairly close to the best lithography method period). We've been in a similar state for CPU's and RAM for decades now. Is there something different about SSD's?
Visualize a single SSD cell as a bucket of electrons. If it's full of electrons, it stands for 1. If it's empty, it stands for 0. Reading this is fast and unambiguous - there's either lots or none. (Single Level Cell type)
Now visualize a bucket that can be filled with no electrons, a third full, two-thirds full, or full of electrons. Now you've got 4 possibilities, so you can encode 2 bits! (Multiple Level Cell type)
Most consumer SSDs use the latter kind, MLC. It's slower to read and the results have to be amplified with better error correction, but you get so much more storage per chip that it's usually worth doing it this way.
The problem is that once you've cranked each of these cells down to 18nm or whatever, you're talking about holding and measuring (at most) 100 electrons per cell. What's that, 0, 33, 66, and 100 electrons? Crank it down even further and you can hold even less.
I think I pulled the numbers out of my ass, but the idea is essentially correct. We're close to the point where it's too difficult and error-prone to get a good read on a cell, requiring too much error correction to make engineering sense and rendering the MLC technique infeasible.
Also going below 18nm is going to be a pain in the ass for other reasons. So it's sort of a mutual dead end.
Another thing I wonder is how much neighboring cells interfere with each other. If that's the case, the most efficient data packing might even rely on bit encodings for multi-cell groups that avoid the combinations that are most likely to cause interference (similar to the 64b/66b encoding in gigabit ethernet, for example) Again, the controller has to do this type of thing already to implement ECC so it seems like a straightforward extension.
Note that I'm not saying that either of these techniques avoid the "dead end" you're talking about -- they're both just ways of squeezing a tiny bit more out of the density/reliability curve at the margins. I'm just imagining how complicated flash controllers might get as they try to capture the last bits of life in the technology.
http://www.anandtech.com/show/5067/understanding-tlc-nand/
http://forums.theregister.co.uk/forum/1/2012/06/25/Chris_Mel...
The concerns in the past have been mainly to do with lithography; eg, when the feature size of the silicon went below the wavelength of the light we were using, we had to make masks that utilized difference patterns. This is a mere manufacturing problem.
But now we're getting to fundamental limits. Even if we had the ability to place the atoms however we wanted them, there's an intrinsic limit. You can't make a transistor out of half an atom.
We already hit a wall with frequency; for the longest time, it looked like speeds would go up and up. It's not an apples to apples comparison, because the Pentium 4 had a long pipeline, but a 3.8ghz Prescott was released in 2005 - which is exactly the maximum turbo frequency of the 2011 Sandy Bridge 2600k I'm typing this now on. Ivy has it beaten by just 100mhz.
Now, that's not to say that computation will stop progressing. But it's not going to look like last year's CPU just smaller for much longer; some pretty fundamental changes are going to have to be made. Dynamically reconfiguring memristor circuits are what excites me, but it's just as likely to be something else instead.
As far as flash memory in particular goes, I'm no expert, but cell durability is falling substantially with each shrink (on average; Intel bucked the trend with their 25nm flash), and so the usable limit to feature size may come more quickly than with standard transistors.
But the industry has managed to push through walls that seemed just as intrinsic before, so I wouldn't bet my life savings on it.
If each layer was 50 nm high, and you built the chip up to an unrealistic 1 centimeter high (eg, a 1 cm^3 chip instead of 1 cm^2), chosen because that would pretty easily fill a 2.5" drive, that would give you:
(1 centimeter) / (50 nanometers) = 200,000 times today's capacity.
Which is only only 18 doublings, or 36 years more of Moore's Law (assuming the pessimistic 24 month end), or roughly the gap between a Commodore 64 and a decent laptop today. Some people still working in the industry have gone through a larger increase. I've gone through a 1000 fold myself, and I'm only 25.
There are sure to be a whole bunch more we can do to get more capacity, but it's pretty mind blowing to think that the theoretical limits to storage are within our lifetimes on an exponential scale. So as much as Moore's law hasn't failed us yet, it certainly will at some point (probably in the form of the doublings themselves exponentially taking longer and longer).
And given that nature has managed to cram this amazing sentient device into a space the size of our skull, using a pretty inefficient design process, I'd say the problem will be not the quantity of the building blocks, but how they're organized :)
That's actually considered to be a feature. http://en.wikipedia.org/wiki/Hyperthymesia
This is true, but the way you wrote it ignores the fundamental problem - it's not we can't make transistors switch any quicker, it's that doing so causes such an increase in temperature that we risk damaging the device. That's why you can read about overclockers using things like liquid nitrogen to run chips at 8 GHz.
Cooling mechanisms like microchannel cold plates and, as we continue with 3D-ICs, interlayer cooling, can allow for higher frequencies.
Gate delays are smaller at low temperatures; those LN2 overclocking runs aren't just fast because of efficient heat dissipation from the CPU, they're fast because the chip is being actively cooled to below room temperature.
So while heat dissipation is a factor, we're also close to the electrical limits as well. Otherwise water cooling (replacing the stock heat spreader) would get closer to LN2 runs. ALUs run at higher frequencies than the rest of the chip, but they're designed to do so (you'd have to shorten the gate pathways like a P4 to do that to the entire chip).
But ultimately, performance per watt is almost universally optimised for these days. It's critical in servers, laptops, mobile phones - The demand for 6ghz, 300W CPUs would be limited to workstation chips, even though we could probably engineer them to be reliable.
Power consumption is always going to increase super linearly with respect to frequency, probably as a fundamental property of any method of computation we use.
I believe though that limit is well below 18 nm. Last I heard, they'd done a transistor with 1.5nm, and they weren't saying that was the limit. I'm not sure what the magic is with 18nm, but I'd sure like to know.
SSD is definitely one of the best upgrades I've ever purchased for a computer.
Since newer Macs doesn't allow for an SSD change, the initial SSD price is very important. I suspect that the fact that you have to max out your SSD on purchase if you want to use your Mac for a longer time, SSDs in Macs have actually become more expensive.
In the past, you could buy a Mac with a small SSD or even a HDD. After one or two years, you could replace your small SSD or your HDD with an up-to-date SSD and could usually benefit from lower storage prices …
For iMac and MacBook Air, upgrade options are available but they are pricey and non-trivial.
I wished I'd waited a bit, as switching again to a 512 would be... I dunno - not sure if it would be worth it again, but I am running out of room a lot on a 256.
http://www.compusa.com/applications/SearchTools/search.asp?k...
But others manufacturers sub 500g are coming down: http://www.compusa.com/applications/Category/guidedSearch.as...
have one in my late 2011 mbp... working great
I wager it would look mostly the same. The reason I say this is because there would still be a distinction between the CPU's memory, the system memory, and then "disk". So long as the IO hierarchy exists, I wager the OS design would more or less be the same.
Now, when memristors come about which have compute+massive memory, then we will need a new OS.
The next great performance challenge may be the so-called "memory wall" wrt the performance of CPUs vs the performance of RAM. Id be curious to see what that would do to performance if it underwent the same dramatic improvement as nonvolatile storage.
The possibilities that could be opened up by having a terabyte or more of extremely fast non volatile storage attached by a bus as large as you care to make it directly on top of a CPU are mind boggling.
Then when you consider that you can use them as FPGAs for computation instead and dynamically reconfigure them... wow.
Memristors are only a year or two away from commercial availability, though it will probably be a while after that until they live up to the hype. We live in exciting times.
The talk:
1. no doubt latency etc are much better for RAM.
Amazon S3 pricing starts at $0.125 per GB per month. So if you just want to store an extra 500 GB that's gonna run $62.50 per month on a HDD!
Given SSDs are 5-10X more expensive who would be willing to pay $300-$600 per month?
Serious question: Any S3 users out there who would pay 5X as much for better performance? If so, what are you working on?
http://www.isuppli.com/Memory-and-Storage/News/Pages/Hard-Di...
(They actually have SSDs, but they're not competitive in the consumer market. See http://www.seagate.com/internal-hard-drives/solid-state-hybr... and http://wd.com/en/products/solidstate/embedded/ )
A lot of the SSD companies aren't really making that much money. The fabs to make the memory chips are huge capital investments and suppliers have historically been bad at managing supply and demand leading to volatile pricing.
Hence the current drop in prices cited in the original article.
Getting a rMBPro with 768GB is $1000 more than the 512 option. Thats just absurd
In the past the sensible option was to buy a Macbook with stock memory / storage and upgrade it yourself, but of course that's no longer possible with the rMBP. Still, that says no more about the actual cost of SSDs than the price of a hotel room says about beds. :)
Seagate has a 4TB disk; they were probably about to release it when the floods hit so I guess they decided to wait.
http://www.amazon.com/OCZ-Technology-2-5-Inch-Performance-OC...
AFAICT, the OCZ Octane is the only 1TB 2.5" drive on the market, but I suspect you'll start to see more of these later this year (at slightly more sensible prices, one would hope).
$1270 for a drive that is essentially a RAID-0 of two 512GB SSDs, packaged in a single 2.5" drive. OCZ also has the Colossus drives that offer 1TB as a RAID-0.
EDIT: Also, at the end of 2009, TRIM support was just hitting the market, and SandForce-based drives were just being announced. Since then, TRIM has become universal, as has 6Gbps SATA support, and most controllers have been through at least one other iteration. SSD caching has also hit the market in a variety of forms.
3 years is a really long time for an entire industry to be totally stagnant. It's somewhat similar to how Intel has been sitting on their asses for the past few years ignoring the entire mobile computing revolution.
You seem to be under the false impression that the NAND is the most important part of an SSD. It's not. From an engineering perspective, it's the least important component - it just happens to be the primary reason for cost scaling with capacity. The controller and it's firmware are far more complicated, and make all the difference for performance. Those components have made a lot of progress in the past three years. And even the NAND has advanced, just not exponentially, because while density is inversely related to unit cost, it is also inversely related to durability, and the drives 3 years ago weren't designed with excessive longevity requirements.