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Comment by kayson | Hacker News Reader

I'm pretty sure Cadence and Synopsys have both released reinforcement-learning-based placing and floor planning tools. How do they compare...?

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Synopsys tools can use ML, but not for the layout itself, rather tuning variables that go into the physical design flow.

> Synopsys DSO.ai autonomously explores multiple design spaces to optimize PPA metrics while minimizing tradeoffs for the target application. It uses AI to navigate the design-technology solution space by automatically adjusting or fine-tuning the inputs to the design (e.g., settings, constraints, process, flow, hierarchy, and library) to find the best PPA targets.

Unfortunately, commercial EDA companies generally have restrictive licensing agreements that prohibit direct public comparison.

Still, the fact that Google uses it for TPU is pretty telling - this is a multi-billion dollar, mission-critical chip design effort, and there's no way they'd make TPU worse just to prop up a research paper. MediaTek's production use is also a good indicator.

They don't. You cannot compare reality (Cadence, Synopsys) with hype (Google).

So you're basically saying that Google should have used existing tools to layout their chip designs, instead of their ML solution, and that these existing tools would have produced even better chips than the ones they are actually manufacturing?

It’s more like no one outside of Google has been able to reproduce Google’s results. And not for lack of trying. So if you’re outside of Google, at this moment, it’s vapor.

> So you're basically saying that Google should have used existing tools to layout their chip designs, instead of their ML solution

Did they tested their ML solution ? With real world chips ? Are there any "benchmarks" that show that their chip performs better ?

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