There is not that much complexity (circuit-wise) in the DRAM array itself apart from the fact that the sense amplifier is essentially an SRAM cell and not really an “amplifier”. Another layer of ridiculous complexity is how to interface that to the outside world without spending the precious die area of DRAM optimized process for complex interface logic or PHYs, so you get the only high-speed single ended parallel bus with weird voltage levels interface that is used in modern computers.