In DRAM tech you can stack several (4-8 at least) HMC memory layers on top of one logic layer.
SSD is moving from 100+ towards 1000 layer memory chips.
By being able to stack logic, it will just change the way designs are made. for example, custom silicon to accelerate a specific operation, for example gzip compression, becomes far more attractive because now there is lots of 'spare' silicon area as long as it remains powered down 99% of the time.
Nope. The yield is relative to the surface area in layers, not the die surface area.
Sure we do. When you actually hit your phone's processor with a non-trivial workload, the die temperature very quickly spikes to near the safe limits for silicon (ie. 90+ °C). It's only if the workload is sustained for a relatively long time (eg. when gaming) that the heat starts to be conducted to the outside of the phone and drive further throttling of the processor to prevent those surfaces from reaching temperatures that aren't safe for human hands. Even when a phone is heat-soaked enough that it is enforcing skin temperature limits, there's still a much higher temperature at the die.
> It is also not more expensive per area to stack logic: by lowering the area of each die, you increase the yield of each in the stack.
The stacking process itself does not have perfect yield, even when assembling known-good dies. Every layer added increases the risk of the stack as a whole becoming non-functional. 3D stacked DRAM has mostly been limited to single-digit stack heights, despite being the easy case for die stacking: every die is the same, has a more or less identical workload (and thus similar thermal expansion) and uses the same interface with the same TSV locations. Most of that goes out the window if you're trying to make a large stack of various co-processors.
You don’t burn active power?
It will increase the heat density of the memory, but there's room to play there. Plus there are some designs that use analog electronics for compute, and it reduces power.
I don't think this is something that actually exists in a working competitive state. I also don't think there is "more attention" by anyone actually working on cpus.
You don’t burn active power?
What does this mean?
What if you put some of these 3D transistors tightly integrated with a 3D SSD and power gated them?
It seems like you would beat the memory wall.
Obviously manufacturing that is beyond us today.
I don't know what this is supposed to mean.
Why would putting coprocessing somewhere outside of the CPU be better than just sending data to storage?
Also wouldn't this idea just be moving data before it's fully processed? Why wouldn't the intermediate data be bigger?
Also "a lot" isn't a number and what are you comparing it to?
- data that is moved is about 100x higher power than data that is local
You have a good point about intermediate data. This would not apply to all algorithms.
Some kind of supercritical CO2 heatspreader with direct die fluid contact perhaps?
Does this increase capacity, performance or both? I'm by no means a hardware guru.