> I wonder: if my sentiment from
https://news.ycombinator.com/item?id=41587866 is correct and Intel is essentially giving up on innovation in chip fabrication
Ignore HN. Almost every commenter on here is well outside of their depth.
Intel's been putting a significant amount of money into adopting High NA EUV in 18A, which is bleeding edge enough for a decade.
Furthermore, even though TSMC and Fabrication have become hot words on HN recently, it has been a financial dead end for almost 15 years now. This is why TSMC, UMC, and Samsung cornered the chip fabrication market - the margins are very very low and the upfront costs are very very high.
There are 3 core processes to bringing a chip to market
- Design: high margins, low capex, this is where American players like Nvidia, AMD, Intel, Qualcomm, etc really shine as well as their Israeli and Indian offices. This is also basically software at this point, as almost all design is done via EDA/ECAD
- Fabrication: Fabricating the aforementioned designed chips. low margins, high capex, commodified due to Taiwanese and South Korean industrial policy along with recent advances in China for 28nm processes, recently prioritized in the US due to COVID era chip shocks
- Packaging and Testing: packaging fabricated chips. low margins, high capex, commodified due to Malaysian, Thai, Chinese, South Korean, Japanese industrial policy, recently prioritized in the US due to COVID era chips shock.
Before the mid-2010s, American companies like AMD, Intel, and IBM Microelectronics used to do all 3, but the low margins of Fabrication and Packaging caused players like IBM Microelectronics and AMD to almost go bankrupt, forcing both of them to divest their fabrication and packaging capacity to a spinoff called GlobalFoundaries. Intel kept their packaging and fabrication capacity, but it has a negative impact on Intel's R&D capacity in the 2010s.
Now with CHIPS Act money, Intel is modernizing it's fabrication and packaging offerings, and splitting them off into "Intel Foundary Services" while keeping design under "Intel".
There are a lot more intricacies as well (bleeding edge nodes vs lagging nodes, analog chips, memory chips, the entire EDA tooling chain, etc) with entirely distinct market dynamics that deserve a paper unto themselves, but that's a long story and I really really hate HN.