I can understand these kinds of faux benchmarks and whitepapers to convince pointy haired bosses to switch between mature, mainstream technologies.
But the early adopters of fringe technology like this are going to be companies with specific needs, and those making the decisions are going to be highly technical. Not to generalize, but they (me included) love details and possibilities, and abhor marketing puffery.
Calxeda should be sketching out novel ways to use the interconnect bandwidth to solve hard problems, with power efficiency x86 can't touch. Not running ab against an ARM core and misinterpreting the results. Sheesh.
A ToR switch will slow you down to 2000-3500ns.
Tilera TilePro64, 64 core 866MHz 22W, 1.7Tbps core-to-core, 46ns L1/L2 miss found in adjacent core, four XAUI (40 Gbps).
When compared to Tilera, Calxeda has a high bandwith per compute ratio. But 200ns core-to-core is not as fast as 46ns.
Tilera also has higher core/watt ratio.
Support for 16GB DDR3/3L memory via four (4) mini-DIMM sockets – one socket dedicated per SoC supports up to 4GB of ECC memory (supplied separately)
Which really doesn't sound as if the memory is shared, to me.