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Comment by jiggawatts | Hacker News Reader

There are fundamental reasons for OS threads being slow, mostly to do with processor design. Changing the silicon would be hundreds of times more expensive than solving the problem in software in user mode.

This is a billion-dollar solution to a hundred-billion dollar problem.

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There is a history of trying to support context switching in CPU hardware. That was a hot idea decades ago. Intel had call gates and some other stuff. Some of the RISC machines had hardware to spill all the registers to memory in background. Some early machines, from the days where CPUs were slower than memory, just had a context pointer in hardware. Change that and you're running a different thread.

None of this helped all that much. Vanilla hardware won out. This is to some extent a consequence of C winning. C likes a single flat address space.

> a consequence of C winning. C likes a single flat address space.

Interesting.

What other language did C beat? How was their address space handling different?

C allows casting to (void *). That implies all pointers are in the same address space. Segmented architectures, where that's not true, have mostly died out. Burroughs used to build segmented address space machines where an address was a path, something like programname/scopename/variablename[subscript]. IBM's System 38 had an "object" architecture. Both worked fine, but were not very C-compatible.

Thanks.

One interesting angle is Mill (note, vaporware). Their "portal" calls between security boundaries are essentially the same as their EBB function calls.

https://www.youtube.com/watch?v=XJasE5aOHSw

Mill is still vaporware. As far as I can tell, they’ve never made anything from silicon.

Compare their progress to RISC-V, which started later and is now shipping in hundreds of products at volume.

Yeah, Mill hasn't been able to find funding to go beyond simulator+compiler+thoughts about FPGA.

Compared to Mill, RISC-V is nearly identical to Arm and X86-64.

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