> what or where does that follow from? One can take a CCD with 2+ cores and pin a process to a set (of the fastest) cores based on profiling the cores and those 2+ cores could use the L3 cache as needed
You're assuming that the buyer knows how to do this and wants to do it themselves, rather than buying a piece of hardware which is configured from the factory to do it for them, and getting a modest discount over the processor with more of the cores operational because some of the cores they weren't going to use anyway might be defective.
> disabling cores at the hardware level is the waste as if they were not disabled, then that would allow other processes to be able to benefit from more than 2 cores to run when desired.
This is exactly the thing some buyers want to avoid. Many applications will spawn a thread for each hardware thread, but each thread for each application will consume shared resources like L3 cache and memory bandwidth. That adds up fast if you have 96 cores per socket. When these are your bottleneck you don't want to spend your time changing the defaults in every application to not do this, you just want a processor with fewer cores and more L3 cache.
> The latter point of disabling cores for "better [frequency] performance per core Which some people will pay a premium for" is dubious especially for the Epyc server line. If that were true, then there should at least be 4 core or fewer SKUs for desktop Ryzen variant where apps like games are more likely to benefit from the higher clock.
Base clocks are limited by power. AM4 supplies up to 170W, which is sufficient to run 12 cores at a base clock of 4.7GHz and is approximately the limit of the architecture rather than the socket. The Zen4 processors with fewer cores than that don't have higher base clocks, they have lower TDPs.
SP5 supplies up to 400W, but supports up to 12 Zen4 CCDs, which is 96 cores. If you enable all 96 cores then you have ~4W/core rather than ~14W/core, and on top of that the Epyc I/O die is bigger and consumes more power than the I/O die for AM5. The highest base clock with 96 Zen4 cores is the 9684X at 2.55GHz and the full 400W. So if you want a >4GHz base clock you have to reduce the core count, and doing this by reducing the number of cores per CCD leaves you with more L3 cache than reducing the number of CCDs. There is no reason to do the same for AM5 because the lower core count processors already aren't limited by socket power.