I forgot were I saw it but it was an analysis of cache to die size and how it has effectively stopped scaling. Larger cache just means larger chips now.

It sort of makes sense because SRAM cannot have the same transient nature of a calculations transistor. It has to hold the state for longer than one 3 billionth of a second. So it has to be a little more robust.

This is my intuitive take so it could be completely wrong.