Hacker News Reader

Comment by jhallenworld | Hacker News Reader

The Altera merger pain is maybe enlightening.

Altera 10-series FPGAs were massively delayed due to Intel's 10 nm fab problems. But I speculate that there was also a big difference in toolchains, does anyone know for sure? I mean Altera was using TSMC previously, and I presume were using industry standard tools: Cadance / Synopsis. But I would guess Intel was running their fab on home-grown tools... what is the status these days? For example I know for sure that IBM's synthesis was "Booledozer".

It's interesting because maybe Intel will spin out the fab business. But are they immediately ready to become a commercial fab business instead an Intel-only business? What's the toolchain like for Intel fab?

View on HN

The Altera merger was a perfect storm. I could write for pages about what went wrong. But here's a few key things: First FPGA companies have been massively hit and miss with their product - they were perfectly capable of screwing up their next chip all on their own (it's a mutually beneficial duolopy of crapness with Xilinx). Second, when Altera agreed to fab with Intel the deal was written such that Intel could never buy any FPGA company other than Altera, so from day 1 this wasn't "Let's produce this together" it was "Let's line up Intel to buy Altera" and so Altera never had to deliver anything, they just had to wait for the acquisition. Third, Altera were one of Intel's first customers and it turns out that Intel's fab process couldn't make some of the gates that Altera needed, which is why in the end they partitioned off the entirety of the transcievers to a separate tile fab'd by TSMC and sellotaped to the edge of the Stratix 10.

Also just to check your facts on the 10nm fab problems. Intel's first FPGA for Altera was always planned to be 14nm. It was totally trash for reasons entirely within Altera's control (don't rock the boat, just wait for the acquisition to close). And the synergistic products were a dead end. I'm sure the 10nm catastrophe didn't help but really that time would've been well spent unpicking the disaster of Stratix 10.

Oh right, 14 nm.. it was so long ago now :-)

Also I assume that both AMD and Intel bought FPGA companies for FPGA co-processor acceleration opportunities. I don't think this has panned out.. I know Microsoft has their bing FPGA accelerator, but I don't think FPGAs have made any dent in the AI space, and are certainly not essential in any of the hyperscalers. Maybe AMD will sell Xilinx at some point.

>they partitioned off the entirety of the transceivers to a separate tile fab'd by TSMC and sellotaped to the edge of the Stratix 10

awesome.. I could imagine it was too risky to redesign the transceivers.

Historically Intel did use non-standard EDA tools which is one reason they had trouble getting outside customers onto 10 nm (besides the fact that 10 nm didn't work). Some Intel acquisitions like Fulcrum and Barefoot never used Intel fabs.

I think they're supporting a more standard toolchain starting with 18A.

I see, this is their newest node or close to it.

https://www.anandtech.com/show/21504/intel-18a-status-update...

"For Intel, getting an external PDK out for a leading-edge process node is no small feat, as the company has spent decades operating its fabs for the benefit of its internal product design teams. A useful PDK for external customers – and really, a useful fab environment altogether – not only needs process nodes that stick to their specifications rather than making bespoke adjustments, but it means that Intel needs to document and define all of this in a useful, industry standard fashion. One of the major failings of Intel’s previous efforts to get into the contract foundry business, besides being half-hearted efforts overall, is that they didn’t author PDKs that external companies could easily use. "

But some bad news today:

https://www.reuters.com/technology/intel-manufacturing-busin...

Reply on news.ycombinator.com