Ask HN: Moore's Law and chip design, what next?
Now that we have TinyTapeout, and the design and development of small custom chips is within the grasp of almost anyone, what new directions do you think chip design will take?
I suspect, but do not know for sure, that verilog is going to emerge as the root cause for a wide variety of cost and error problems in silicon design. I'm therefore interested in non-verilog approaches to describing chips, but only at the casual / hobby level for now.
If you want to route things yourself, I suppose you could use their new analog pin support, for which they gate power to keep the rest of the chip safe.