RuyiBook the first laptop powered by a open-source RISC-V processor
milkv.io
milkv.io
You can download and simulate it on regular hardware.
I ran a few micro benchmarks it XiangShanV2 (Nanhu, the one in the laptop) and XiangShanV3 the next generation of their implementation:
integer micro benchmark from the XiangShan repo:
Zen1 1600x XiangShanV2 XiangShanV3
Quick sort: 16833 cycles 11122 cycles 10582 cycles
Queen placement: 56606 cycles 59712 cycles 49912 cycles
Brainf**k interpreter: 132821 cycles 113686 cycles 52676 cycles
Fibonacci number: 7473 cycles 5999 cycles 2763 cycles
Eratosthenes sieve: 5364 cycles 3140 cycles 2037 cycles
A* 15-puzzle search: 20459 cycles 14626 cycles 11018 cycles
Dinic's maxflow algorithm: 12357 cycles 11184 cycles 6174 cycles
Lzip compression: 7140 cycles 5932 cycles 2289 cycles
Suffix sort: 16316 cycles 14967 cycles 11256 cycles
MD5 digest: 5882 cycles 3793 cycles 1997 cycles
Total: 281251 cycles 244161 cycles 150704 cycles
scalar fp32 mandelbrot 64x64 with 64 iterations:
Zen1 1600x: 1264882 cycles
XiangShanV2: 1361856 cycles
XiangShanV3: 1011363 cycles
At the same clock frequency XiangShanV2 is quite competitive with the Zen1 CPU, however it doesn't implement the RISC-V vector extension, so will be a lot slower in any SIMD workloads. The RuyiBook is supposed to clock at 2.5GHz, but there were slides saying it can go up to 2.8GHz, while the 1600X can go up to 3.7GHz.
XiangShanV3 is a lot faster, and does implement the RISC-V vector extension, as well the hypervisor extension. They also target a 3GHz frequency.
Here is a recent presentation of XiangShanV2 micro architectural implementation details: https://raw.githubusercontent.com/OpenXiangShan/XiangShan-do...
There were a few talks at RISC-V Summit Chine regarding XiangShanV3 implementation details. Here is a recording, look at the second Day 2, if the clunky interface works for you: https://www.c114.com.cn/live/t850.html
They also present at this years hotchips in a few days.
In applications processors chips about to come out in the next 12 months, such as this XiangShan and the SG2380, are getting up into the performance level of 10 year old Zen and Core i5 etc, which is still a perfectly fine performance level for many people and uses.
Linux has been available for RISC-V for many years, a number of distros have 2nd tier support for RISC-V, probably moving to 1st tier soon.
Android is working towards 1st class support for RISC-V, with the desired ISA extensions, fast enough hardware, and full software porting looking to converge into competitive products around 2026-2027.
Arm is NOT a "common ISA". It is proprietary and support can be arbitrarily removed at any time. Since 2023, Arm's highest performance CPU cores have dropped support for the 32 bit ISA(s) even for user programs. That's orphaning an almost 40 year history of 32 bit Arm software, restricting it to being used only on legacy CPUs which will rapidly have much less performance than newer high end CPUs.
At the same time, the low end Arm microcontroller family remains 32 bit only. And the 32 bit and 64 bit ISAs are totally different to each other.
RISC-V vendors on the other hand are happy to license you a 64 bit core with Cortex-M0 or Cortex-M3 size and features. These are often valuable as a control processor in a bigger chip with 64 bit applications processors and >32 bit address space.
In RISC-V the 32 bit and 64 bit ISAs are almost identical and it's very cheap and easy to support 32 bit code on a 64 bit CPU -- the RISC-V spec fully supports this, though demand is low as there is not yet a lot of legacy 32 bit RISC-V code. Most current RISC-V CPU cores don't support this, though for example the THead C908 does.
It's probably 20-30 billion by now.
And actually no one really knows the total because no one is required to report that they are using RISC-V, let alone sales or production numbers.
It comes down to adding up those companies that have said. WD/Sandisk are shipping several billion a year, and started early (even before the formal spec). Samsung said in 2019 that the Galaxy S20 had two RISC-V cores in every phone. They are now publicly known to be porting their Tizen OS and the DotNet language execution environment to RISC-V, for use in TVs and "other unspecified products". They ship quite a lot of stuff. LG are also known to be switching to RISC-V. Qualcomm have a handful of headline Arm applications processors in chips such as the Snapdragon series, and possibly a dozen or more unannounced RISC-V CPUs in the same chips.
But "displacement" does not mean installed base of CPUs or even current sales of CPUs in existing products. It is not even about new products that use existing chips.
"Displacement" means the proportion of new chip design wins, which over the long term feed through to the above measures.
Both Andes and SiFive have probably individually (and certainly combined) for several years now had more new design wins for CPUs in new chips than Arm.
There are an increasing number of formerly skeptical manufacturers putting both an Arm core and a RISC-V core in the same chip, the most well-known example recently being Raspberry Pi, a company that is simply full of ex-Arm and Arm-centric Broadcom employees.
The 10b+ cores by December 2022 were fabricated and deployed physical cores inside physical chips, brucehoult was responding to your non-sourced "There are 100 billion embedded ARM processors in operation" statement.
Of course this number is much larger now, as RISC-V adoption has exploded. RISC-V is not a fad that will go away overnight. It has long entrenched itself very deeply in this industry.