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Comment by raverbashing | Hacker News Reader

It's probably going to be a small RTOS in each core

Or like it's done in PS3, where you have one core scheduling the others

"but can I install node.js on each core?" maybe, but that's really not the idea

You can go the RTOS route, but each card looks like a 50-core, 200-thread machine with 8 GB of GDDR5 memory and can comfortably run a Linux or *BSD stack.

In fact, I'd love to see developers using them as their personal machines (Intel would probably have to make ATX motherboards with it) so that more and more software makes use of the more and more available threads on our own machines. An entry-level laptop these days looks like 8 processors to the OS and this number will only go up.

While these are x86 cores, and clearly capable of running desktop software, it wouldn't be a good experience as the primary CPU. The circuit size almost certainly means that these are in-order CPUs, probably with minimal superscalar capability, and likely a shallow pipeline. So scalar code is going to run terribly on them. Desktop usage is dominated by scalar CPU overhead.

That's precisely why it would be interesting - developers would have to work around these limitations. Number of cores will continue to go up and, if the software allows it, they can be simples ones.

With all due respect: yawn. People have been predicting the end of scalar code now for a decade, and it's no closer than it was. Show me a SIMD Javascript interpreter, or DOM layout engine, or SSL implementation, or compression algorithm, or heap allocator, or...

Won't happen. Out of order, heavily superscalar, deeply pipelined cores have won in the market because they're better for 90% of the problems you will see. But there are better architectures for the remaining 10% (and of those, "3D games", "Bitcoin mining" and "Password cracking" seem to make up about 90%), so you'll see lots of churn in this space as people try to figure out the best and most future-proof architeture.

For me, I like this a lot. The Knight's Corner architecture looks mostly identical to the AVX code you can run on Sandy/Ivy bridge right now, just with a few new features and a different SIMD width. From a programmer's perspective, it's much cleaner than the hidden-behind-multiply-abstracted-layers-above-proprietary-secret-hardware nonsense being peddled by AMD and NVIDIA.

But it won't run your desktop. Ever. Sorry.

I agree it won't run current applications (as in Eclipse, Word, Excel, Emacs) much better than current CPUs do. But I can, for instance, imagine a huge number of applications that cannot run well on current architectures that would benefit from having a huge number of relatively simple cores.

My notebook currently has two kinds of cores - 2 amd64 ones and I don't know how many really dumb GPU cores. It would be great if my Gmail experience were snappier when I'm not dragging windows between monitors.

The first multi-processor machine (a 4-processor Pentium Pro) I used didn't impress me by being fast (it was, but not that much). It impressed me by being much smoother under load than my previous computer. It doesn't matter how sure you are it won't happen, it eventually will.

I agree with almost everything you said, but I take issue with a couple of your examples. First, depending on the cipher suite, SSL can in fact get significant speedups from SIMD. Second, while compression is a pretty serial task, if you compress in blocks, then you can parallelize across those blocks; I know that's not SIMD, but it also doesn't require fancy processor cores to take advantage of the parallelism. A lot of server tasks are similar to that: parallel enough that they could benefit from having a bunch of somewhat wimpy but power-efficient cores thrown at them.

ok whats the idea then, how am I supposed to program the tiny machines/cores?

Have a look at OpenCL, I think you will use OpenCL or a similar framework to code for this device.

Have a look at http://ispc.github.com/ -

Intel SPMD Program Compiler

"An open-source compiler for high-performance SIMD programming on the CPU"

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