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Comment by taylodl | Hacker News Reader

> Why didn’t ternary computing catch on? The primary reason was convention. Even though Soviet scientists were building ternary devices, the rest of the world focused on developing hardware and software based on switching circuits — the foundation of binary computing. Binary was easier to implement.

That's not the way I've heard the story. Ternary isn't just on/off, voltage yes/no like binary - you need to know the charge of the voltage: is it positive or negative? Essentially then your circuits are -/0/+ instead of (0/+) like it is for binary. Such ternary circuits resisted miniaturization. At a certain point the - and + circuits cross and arc and create a fire. The binary circuits kept getting miniaturized.

The story I've heard that goes along with this is that's how the US ultimately won the space race: the US bet on binary computing and the Soviets bet on ternary computing. The Soviets lost.

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I always thought the information density advantage of ternary disappeared once you put it in the real world:

- harder to discriminate values as you pack more in the same dynamic range

- more susceptible to noise

- requires lower clock rates for (wired) transmission

- requires more complex protocols for (wireless) transmission

- representing 0 or 1 as switched states uses "no" power, but getting a switch to be "halfway on" uses a lot of power

But most transmission systems use multi-level signals. Gigabit Ethernet uses PAM-5, the latest versions of PCIe use PAM-4, and USB 4 uses PAM-3. Not to mention the crazy stuff like QAM-256 and higher.

This doesn't make sense to me. You don't have to use negative voltages to encode ternary. You can just use three different positive voltages, if you like. 0V = 0, +3V = 1, +6V = 2.

That's my understanding as well. Voltages are relative, you are free to choose a "ground" and work with negatives or not if you want.

Practically it is convenient I think if your ground is third little round prong on the power cord.

I wonder if this is why they suggested a negative voltage. Even though voltages are secretly relative under the hood, it seems like it could simplify things to have two directionally different voltages.

Many reasons. For example, using negative voltage will reduce DC component in the wires, that will improve reliability over long lines, as now all you need is to sense the polarity of the signal, not the level. You'd also need high power reference voltage (for "1") wire going all over the board, which will be nasty polluted with uncorrelated switching noise, will sag in uncorellated way with respect to the "2" (Vcc wire) etc.

Well, this is stuff I read 40 years ago about tech nearly 30 years prior!

They might not have had the third prong back then :)

Except in the analog world its not so clear, you can't just say +3V=1. What if its 3.7V? or 4.5V? Early tools weren't that accurate either so you needed more range to deal with it.

It should be stated as ranges for clarity. It’s never an absolute voltage (quantum mechanics itself won’t round that nicely). Although this is also true of binary. >x volts = 1 otherwise 0 volt n binary. Same thing in ternary just with 3 ranges.

Yeah at some point you have to deal with the transition between the clean conceptual world of digit computing and deal with the fact a circuit can't instantly transition between 0v and 3.3v/5v/whatever level your signal operates at.

Indeed that's how nearly all NAND flash works nowadays, early SLC media was binary with each cell set to a low or high voltage, but as density increased they started using more voltages inbetween to encode multiple bits per cell. The current densest NAND uses 16 different positive voltage states to encode 4 bits per cell.

> The current densest NAND uses 16 different positive voltage states to encode 4 bits per cell.

Wait, what?! I did not know this. Is there a link where I can learn more?

https://en.wikipedia.org/wiki/Multi-level_cell

Very interesting. I would have thought the overhead from the memory controller would negate all savings, but I know very little about modern cell design.

> overhead from the memory controller

If you want to do it in a single step, you need 8 analogic comparators at the output of the memory, and one level of "and" and "or" gates to solve each bit.

Most ADCs use a single comparator + OpAmp and convert the value in 3 steps. But that would make your memory slower.

Either way, the task of converting it does not fall over the controller.

https://www.anandtech.com/show/5067/understanding-tlc-nand

That's an older article from when TLC (3bit) NAND launched, but the principles are the same for QLC (4bit).

Nowadays SLC and MLC are barely used because TLC is good enough for nearly all purposes.

> Nowadays SLC and MLC are barely used because TLC is good enough for nearly all purposes.

This is very interesting. Thank you.

Most "SLC" and "MLC" that's sold is actually TLC/QLC hardware that's only using a subset of the voltage levels available. It ends up being significantly cheaper due to the economies of scale in manufacturing.

Yep, if you ever come accross the term "pSLC" (Pseudo-SLC) that means the underlying hardware is capable of running in MLC/TLC/QLC mode, but the controller firmware has been configured to only use the lowest and highest voltage state in each cell.

Some SSD controllers will also reassign regions of flash to different modes on the fly, the drives unused capacity can be used internally as a very fast pSLC write cache, and then as the drive fills up those cells incrementally get switched over to the native TLC/QLC mode.

Does this mean that in some cases damaged QCL "sectors" could be still used as a SCL?

So each cell is a nibble. That's cool

The main problem is that if you are minimizing the voltage to the minimum that can be safely distinguished for binary, you must, by necessity, be introducing twice that voltage to introduce another level. You can't just cut your already-minimized voltage in half to introduce another level; you already minimized the voltage for binary.

50 years ago this may not have been such a problem, but now that we care a lot, lot more about the power consumption of our computing, and a lot of that power consumption is based on voltage (and IIRC often super-linearly), so a tech that requires us to introduce additional voltage levels pervasively to our chips is basically disqualified from the very start. You're not sticking one of these in your server farm, phone, or laptop anytime soon.

Voltages are always measure relative to each other. In ops example -3V to +3V has 6V difference just as 0V to 6V does and the arcing is the same.

Op didn’t specify any particular voltage but you should get the example. You need more voltage between the highest and lower states to differentiate the signals compared to binary. It can work well but only in circuits where there’s already very low leakage (flash mentioned as another reply is a great example).

While true, being negative in a semiconductor system is very relevant though because any P-N junction is a diode. So your ability to propagate current (and thus downstream voltages) does depend on the voltages all pointing the right direction.

note: I am aware that strictly speaking a CPU isn't transistors, but it is a lot of variously doped silicon still.

Yes, but then you have to use a lot more complex electronics and production tolerances, as now you'd need to either distribute voltage reference for intermediate level all over the board, which essentially makes it exactly same system as with negative voltage, but with the third wire becoming ground; the same concept but worse implementation, or make circuits able able to discriminate between two different levels, this will be both difficult in terms of implementing the circuit, and will also lead to enormous energy waste, as part of your transistors will have to be half open (jinda similar similar to ECL logic, but worse).

> At a certain point the - and + circuits cross and arc and create a fire.

That's not unique to ternary circuits. That's just how voltage differential of any kind works.

The trick is figuring out how many states you can reliably support below the maximum voltage differential the material supports. As we reach the physical limits of miniaturization, "two states" is almost certainly not going to remain the optimal choice.

I am extremely doubtful about your last claim; is there work being done in that direction that you can point to? Don't get me wrong, it would really be exciting if we could get actual efficiencies by increasing the number of states, but all the experts I have talked to so far are very pessimistic about the possibility. The problems introduced by ternary circuits seem to offset any claimed efficiency.

Does MLC flash count as a limited example?

I think this sentence from the Space Race Wikipedia is funny:

> The conclusion of Apollo 11 is regarded by many Americans as ending the Space Race with an American victory.

"Winning the space race" is a rather woolly concept and depends on your definitions. Although NASA did land astronauts on the moon, the Soviets had firsts in most of the main areas relevant today (first satellite, first astronaut, first space station, first landing on another planet, etc etc.).

https://en.m.wikipedia.org/wiki/Timeline_of_the_Space_Race

It's easier to win the space race if you are allowed to define your own winning criterion/criteria. :-)

The key is to pick a winning criteria that is sufficiently meaningful looking and then really sell the heck out of it.

There were lots of good arguments for the Soviet space program having been ahead, lots of landmarks they hit first. But, ya know, the dude standing on the moon couldn’t hear these arguments.

> The key is to pick a winning criteria that is sufficiently meaningful looking and then really sell the heck out of it.

Exactly. :-)

1st to anything is considered a significant metric, it's simply picking the larger tasks and working your way down to possibility to find effective goals.

Don't disagree with you, but, so far, the US is the only country to land people on the moon - and they first pulled that feat off 55 years ago!

Of course, it's not clear whether they could pull that feat off right now, today, but they did pull it off and nobody else has. Suddenly nobody remembered the Soviet accomplishments of first satellite in space, first man in space and so forth. All they remember and care about is first man to the moon.

After all, America does a great job of marketing herself! :)

America landing on the moon signaled the end of the "space race". The soviets could have pushed more money into it and landed one of their cosmonauts on the moon, but they just gave up because to them "the race" was lost, and not worth putting so much more money to come in second-place. All their other "firsts" were like trial/qualifying runs for the big race of landing on the moon.

That's pretty much the way I understand it. I'm sure the Soviets could have landed a cosmonaut on the moon in the early-to-mid 70s, but why bother? It would actually look lame! Hey! We can put men on the moon, too!

There is an effort to put the first woman on the moon, but as far as I can tell, the US is the only country concerned with that. Too bad, because that title has been there for the taking for over 50 years now.

> At a certain point the - and + circuits cross and arc and create a fire.

To do binary logic we do CMOS. The reason CMOS gets hot is because the complementary transistors don't switch at the same time. So, at a certain point, the Vss and Vdd circuits connect and create a massive current drain.

> The binary circuits kept getting miniaturized.

Sure.. but they're not getting much faster.

There are three loss mechanisms for CMOS. a) Leakage b) Crossing current c) Ohmic losses because of currents required to charge/discharge capacitances (of the gates etc..)

Pretty sure c) dominates for high frequency/low power applications like CPUs, as it's quadratic.

I think it is yet another "bears walking on redsqare" level of claim (I mean about ternary systems). There was only one minor ternary computer produced by USSR ("Setun"); it has never been a big thing.

SETUN itself was an electronically binary machine that used bit pairs to encode ternary digits[1].

In support of your point, of the Soviet computers surveyed in the cited article, six were pure binary, two used binary-coded decimal numerics, and only SETUN was ternary[2].

[1] [Willis p. 149]https://dl.acm.org/doi/pdf/10.1145/367149.1047530#page=19

[2] [Willis p. 144]https://dl.acm.org/doi/pdf/10.1145/367149.1047530#page=14

[Willis] Willis H. Ware. 1960. Soviet Computer Technology–1959. Commun. ACM 3, 3 (March 1960), 131–166. DOI:https://doi.org/10.1145/367149.1047530

Complete fabrication, with blatant disregard for physics and electronics.

Many modern CPUs use different voltage levels for certain components, and everything works fine.

>> Many modern CPUs use different voltage levels for certain components, and everything works fine.

But none of them use more than 2 states. If you've got a circuit at 0.9V or one at 2.5V they both have a single threshold (determined by device physics) that determines the binary 1 or 0 state and voltages tend toward 0 or that upper supply voltage. There is no analog or level-based behavior. A transistor is either on or off - anything in the middle has resistance and leads to extra power dissipation.

Isn't high speed signalling full of examples for multi level (as in, more-than-two level) signals? PCI-E's gen 6 and the various wireless standards come to mind.

In limited, specialized domains where big chunky (comparatively) transceivers let you abuse "actually analog" naturę of the medium for higher speeds.

Not for internal logic.

At least as things stand now, these signals are only used when absolutely necessary, and no real work is done on them directly. Transmitting many bits in parallel was the original way of doing this, and would still be preferred if feasible, but timing issues arise at modern speeds over long distances (10s of cm). So the signals on one board, which are still binary and parallel, are multiplexed into a multi-level serial signal before transmission, transmitted over the serial data lines, and then received and demultiplexed on the other board from multi-level serial back into binary parallel signals. All computation (logic and arithmetic) operates on the binary signals, not the multi-level signals.

> various wireless standards

Electromagnetic waves do not interact with one another, so it is difficult to build a transistor with it. There's some research into optical transistors but doesn't seem to work well yet.

Another comment suggest that NAND chips use 8 different voltages / states to encode 3 bits just in voltage states.

For data storage, not computation.

I don't really understand that distinction?

What makes data storage inherently different on the gate level?

Solving that issue has some characteristics that makes multistate voltage a good choice, but sure, that is the circumstances under whish you would use it.

Yes, and there is considerable electronics required in the readout logic to make sure that they are identified correctly, including error correction. That's not practicable for anything but storage or maybe off-chip/high-speed connections.

Actually, I have to correct myself. Charge levels, not voltage levels, and you do not necessarily need to have multiple voltage levels on the driving side to set these charge levels, you can do it by varying the write time.

As mentioned by another comment, NAND has multiple voltage levels.

   - Single-level cell (SLC) flash: One bit per cell, two possible voltage states
   - Multi-level cell (MLC) flash: Two bits per cell, four possible voltage states
   - Triple-level cell (TLC) flash: Three bits per cell, eight possible voltage states
   - Quad-level cell (QLC) flash: Four bits per cell, 16 possible voltage states

NAND flash is so-named because of its physical resemblance to a NAND gate, but I don't think it actually functions as a NAND gate.

Put another way, is it possible to feed two 16-level signals (X and Y) into a QLC and get a 16-level result back out of it (Z), where Z = X NAND Y, and if so, is it significantly faster, smaller, or less power-hungry than 4 conventional NAND gates running in parallel? I don't think so.

As it stands, NAND flash cells are only used for storage, and that's because of their high information density, not any computational benefits. Once the signals leave the SSD, they've already been converted to binary.

> is it significantly faster, smaller, or less power-hungry than 4 conventional NAND gates running in parallel?

It's not implemented any one of these several manners just for the hell of it. Everything has tradeoffs (which vary with each manufacturing node, architecture and timing in the market price landscape). The engineering and product management teams are not throwing darts. Most of the time anyway.

Saying that it's still binary because you feed binary into the chip and get binary back is moving the goal post (imo). A multilevel subsystem in a larger one is still multilevel, an analog one is still analog, an optical one is still optical (see switching fabric recently.)

So anyway, the russian systems did explore what could be done. The flash storage does answer some favorable tradeoff. And so have countless university projects. Including analog neural net attempts.

The second half of that question is not relevant if the answer to the first half of the question is "no" (it wasn't rhetorical). QLC "NAND" is not a logic gate, it is a storage mechanism. It does not compute anything.

Modern magnetic hard drives use all sorts of analog tricks to increase information density but few would seriously argue that this constitutes a fundamentally different kind of computing.

Yes, QLC (etc.) is an innovation for data storage (with tradeoffs). No, it is not a non-binary computer hiding in plain sight.

Fair enough. Common examples in storage and transmission. Not so common in computing for now. The closest obvious computing example, to my mind, is analog neural net blocks meant to be integrated in digital (binary) systems. Not ternary, old school (hah!) analog.

NAND flash has multiple different charge levels. This doesn't necessarily require different voltage levels.

Not agreeing with the parent post, but the different domains in modern electronics only work because they're (nominally) isolated except for level crossing circuits.

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