Wow, this seems to address every complaint about the RP2040 I had. Be sure to read all the way to the bottom for the "One more thing" section. You can choose Cortex-M33 or RISC-V at boot time transparently!
Making a single core with two instruction decoders but a shared register file, caches, prediction logic and ALU would make sense for a very high-end application processor type core, but not for these small devices. You would also need an instruction set license from ARM for that, vs just licensing the M33 netlist.
Supposedly it didn’t require any measurable amount of additional die space, because other things constrained the minimum size of the die (like the I/O pads), according to one of the Raspberry Pi engineers.
An additional ARM core would have required significant changes to the crossbar. Right now, only two cores can be active, not three.
I think this type of pseudo-wasteful design is not unheard of when manufacturer had two markets to deliver to that had substantially different processing, but not I/O, requirements, as well as when some of major features in already manufactured chip didn't work out and ways to offset losses would be nice.