I wonder whether any other ISAs support something similar.

In 32 bit ARM you could get close with variations on a load/store instruction with an offset of 0.

  LDR R0, [R1]
  LDR R0, [R1, #-0]
  LDR R0, [R1, #0]!
  LDR R0, [R1], #0

Same instruction but different addressing modes and therefore different mnemonics.