Reverse engineering XC2064, the first FPGA (2020) | Hacker News Reader

Reverse engineering XC2064, the first FPGA (2020)

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72 pointsvinnyvichy13 comments

I don't know why this popped up on HN after four years, but author here to answer your questions...

It's because someone submitted it and more people voted on it. Things often take time to get randomly noticed by someone who also happens to habitually submit things to HN.

> It's because someone submitted it and more people voted on it.

Well, I can't argue with that :-)

What was the XC2064 used in, as far as like commercially available products or similar, if you know off hand? I know some network cards and things like that have FPGAs.

For example 1995 Snappy Video Snapshot LPT dongle by Paul Montgomery (Newtek co-founder https://en.wikipedia.org/wiki/Paul_Montgomery#Play_Inc.). @TubeTimeUS on twitter did a Snappy deep dive, teardown and reverse engineering down to schematic and figuring out remarked "PLAY HD-1500" main chip is just a XC2064 FPGA. PLL + 30msps ADC + special 2Mbit video ram capable of holding whole field = this thing grabs whole one field of video all at once after perfectly synchronizing to 14.318MHz video clock.

https://threadreaderapp.com/thread/1301990455182155776

wiki: "Snappy was the first mainstream video input device for Windows personal computers, with Play selling over US$25 million of Snappy in its first year.[9] Byte Magazine awarded Snappy its Technical Excellence award in December 1995, stating "Every once in a while, we see a product so impressive, it makes us rethink an entire category. That was certainly the case with Play Inc.'s Snappy."[10]"

NewTek's Video Toaster had three XC2018s.

At one place I worked around 1991-4, we used them for control hardware for synchrotron beamlines. These were produced in a very small numbers (10s of units) so the cost of the FPGAs wasn't a significant problem, unlike mass market products.

At the time we used Altera CPLDs rather than Xilinx. The main differences were: the Xilinx chips needed a small serial ROM located next to the chip to load the bitstream at power-on, whereas the Altera chips used (I guess) some kind of technology similar to EEPROM so they maintained their programming when powered off. The software ecosystem of the two was completely different and a significant lock-in. Once you'd chosen Altera and their Max+Plus II software, the only way to "port" to a Xilinx chip would be to completely reimplement it.

My three reasons:

1) it is vital for earthlings to simplify chip design down to the materials level. XC2064 FPGA best starting point for moving logic away from the CMOS paradigm, it is the simplest yet has all important details. If you are thinking about merging memory and logic, or even excitonic/polaritonic optical switching, XC2064 good to keep in mind?

2) I saw the your other post on the front page

3) Reverse engineering is sacred work, no harm reposting and recelebrating past work, 4 years is nothing on the glacial pace of realigning incentives :)

That said, I have a few questions:

  The XC2064 uses a variety of highly-optimized circuits to implement its logic blocks and routing. This circuitry required a tight layout in order to fit onto the die.

Seems like you might have more info about the optimization details. Do you maybe have access to Ross' design notes or something?

No, I don't have any access to internal design notes. But looking at the layout, it's clear that they went to a lot of work to optimize it.

> XC2064 FPGA best starting point for moving logic away from the CMOS paradigm

What makes you think that? The architecture of the XC2064 is fairly unremarkable; what makes it special is simply that it was Xilinx's first FPGA.

More broadly, what do you mean by "moving logic away from the CMOS paradigm"? Whether you mean that in terms of logic families or something more fundamental, the starting point would probably be a few simple logic gates on a test wafer, not an entire FPGA.

It's remarkably simple (to me, at least)

>moving logic

Oops typo that "logic" isnt supposed to be there.

I meant that its the simplest "complete" system that includes power, memory, i/o, tight integration with software (ie "bitstream format"), etc.

If you already have tooling in place to fabricate logic gates systematically, it's almost trivial to go up to XC2064 level of complexity; you might even want to do that before optimizing your "revolutionary" logic gates. Okay this might again be obvious, but it's exciting, motivational, calming to point that out to "beginners" (often that's what revolutionaries are), who want to know at every step that something close to their API has been mostly validated & they can concentrate on the revolutionary kernel

eg, the other front page threads on how to build very quickly and properly

https://news.ycombinator.com/item?id=41148517

https://news.ycombinator.com/item?id=41150278

How much design-side innovation is there in the FPGA sector? Are modern large FPGAs just scaled up versions of the logic cell grid design of the XC2064 or would those look structurally very different?

The significant difference is modern FPGAs have dedicated blocks for things like static RAM and SERDES. This has the advantage that if you want to, for example, implement a soft CPU core with some registers and a PCIe interface, you don't need to waste large amounts of your general purpose look-up tables implementing those, you can put the registers in a pre-made block of static RAM and the PCIe can be handled by SERDES. In fact modern FPGAs often have ARM cores next to the fabric so you can make hybrid software/hardware designs.

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