Back in the late 70s and 80s, many computers and other digital systems were actually designed using basic blocks similar to this. Since chip layout is by far the biggest expense (especially back then) it made sense to design just one customizable chip, and then produce it with different metal layers to configure it into various arrangements, so it is relatively easily "programmed" just before manufacturing. DEC's ill-fated VAX 9000 was done in this way, probably the last great pre-CMOS processor design, with hundreds of ECL gate array chips all based on a couple die patterns. Unfortunately the benefits of sheer density from CMOS were undeniable. When they crammed the VAX into a $1000 CMOS microprocessor, it outperformed the $1 million VAX 9000 four years later. These days it's relatively uncommon as a technique except for rapid prototyping. With standard cell ASIC designs, a gate array cell able to perform any function is still an option, but modern design tools make it much easier to use more optimized logic.