Hacker News Reader

Comment by hinkley | Hacker News Reader

At this point, especially with backside power, I wonder how much cache stalls on one processor result in less thermal throttling both on that processor and neighboring ones.

Maybe we should just be letting these procs take their little naps?

View on HN

This leads, in the extreme, to the idea of a huge array of very simple cores, which I believe is something that has been tried but never really caught on.

Sounds like gpu to me.

The Xeon Phi was a “manycore” x86 design with lots of tiny CPU cores, something like the original Pentium, but with the addition of 512-bit SIMD and hyperthreading:

https://en.m.wikipedia.org/wiki/Xeon_Phi

IIRC the first Phi has SMT4 in a round robin fashion similar to the Cell PPUs. To make a core run at full speed, you should schedule 4 threads on it.

The very, very first Phi still had its ROPs and texture units, being essentially a failed GPU with identifying marks filed off (yes, the first units were Larrabee prototypes with video outputs unpopulated)

> the first units were Larrabee prototypes with video outputs unpopulated

Such a shame. I'd love to base a workstation on those.

Seems to be a hobby I never quite act upon - to misuse silicon and make it work as a workstation.

GPUs are actually SMT'd to the extreme. For example, Intel's Xe-HPG has 8-wide SMT. Other vendors have even bigger SMT: RDNA2 can have up to 16 threads in flight per core.

That description reminds me of GreenArrays' (https://www.greenarraychips.com) Forth chips that have 144 cores – although they call them "computers" because they're more independent than regular CPU cores, and eg. each has its own memory and so on. Each "computer" is very simple and small – with a 180nm geometry they can cram 8 of them in 1mm^2, and the chip is fairly energy-efficient.

Programming for these chips apparently a bit of a nightmare though. Because the "computers" are so simple, even eg. calculating MD5 turns into a fairly tricky proposition as you have to spread out the algorithm to multiple computers with very small amounts of memory, so something that would be very simple on a more classic processor turns into a very low level multithreaded ordeal

Worth noting that the GreenArrays chip is 15 years old. 144 cores was a BIG DEAL back then. I wonder what a similar architecture compiled with a modern process could achieve. 1440 cores? More?

those weren't "real" cores. you know what current chip has FUs that it falsely calls "cores"? that's right, Nvidia GPUs. I think that's the answer to your question (pushing 20k).

In what way were they not “real” cores? They had their own operating environment completely independent of other cores. GPU execution units on the other hand are SIMD--a single instruction stream.

How are GA144's nodes / "computers" not real cores? They're fully independent, each has its own memory (RAM and ROM), stacks, and registers, its own I/O ports and GPIO pins (some of them), and so on.

https://www.greenarraychips.com/home/documents/greg/PB003-11...

Calling all TIS-100 fans

it's a very interesting product - sort of the lovechild of a 1980s bitsliced microcode system optimized for application-specific pipelines (systolic array, etc).

do you know whehter it's had any serious design wins? I can easily imagine it being interesting for missile guidance, maybe high-speed trading, password cracking/coin mining. you could certainly do AI and GPUs with it, but I'm not sure it would have an advantage, even given the same number of transistors and memory resources.

I think they were more meant to minimize power use than be very performant. Honestly no clue how widely the GA144 is used in real-world applications, but I guess that since the company still exists they have to be getting money from somewhere

Transputers.

Reply on news.ycombinator.com