The AMD Zen 5 Microarcitecure

The original AMD slide deck can be found like this:

https://images.anandtech.com/galleries/9499/AMD%202024_Tech%...

from 01 to 23

https://images.anandtech.com/galleries/9500/AMD%202024_Tech%...

also from 01 to 23

https://images.anandtech.com/galleries/9501/AMD%202024_Tech%...

also from 01 to 23

https://images.anandtech.com/galleries/9502/AMD%202024_Tech%...

from 01 to 31

The last 2 of these 4 presentations (Papermaster & Boppan) are the most interesting, as they give details about the microarchitectures of the CPU/GPU and of the NPU.

The Anandtech article fails to link the fourth gallery and it links only downsized images in the first three galleries.

Looks like Zen 5 will now have 3 integer multiplication ports? Hopefully that yields a reciprocal throughput of 2/3 of sequences of mulx instructions!

EDIT: With the 8-wide dispatch system, I suppose it can actually target Apple's silicon when it comes to asymptotics, no?